feat: implement OneNet communication and ESP8266 integration
break: switch to c8t6
This commit is contained in:
@ -1,6 +1,6 @@
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/**
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******************************************************************************
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* @file stm32f103x6.h
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* @file stm32f103xb.h
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* @author MCD Application Team
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
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* This file contains all the peripheral register's definitions, bits
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@ -29,12 +29,12 @@
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* @{
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*/
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/** @addtogroup stm32f103x6
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/** @addtogroup stm32f103xb
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* @{
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*/
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#ifndef __STM32F103x6_H
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#define __STM32F103x6_H
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#ifndef __STM32F103xB_H
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#define __STM32F103xB_H
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#ifdef __cplusplus
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extern "C" {
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@ -109,11 +109,16 @@ typedef enum
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TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
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TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
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TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
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TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
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I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
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I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
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I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
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I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
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SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
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SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
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USART1_IRQn = 37, /*!< USART1 global Interrupt */
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USART2_IRQn = 38, /*!< USART2 global Interrupt */
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USART3_IRQn = 39, /*!< USART3 global Interrupt */
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EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
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RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
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USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
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@ -565,7 +570,7 @@ typedef struct
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#define FLASH_BASE 0x08000000UL /*!< FLASH base address in the alias region */
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#define FLASH_BANK1_END 0x08007FFFUL /*!< FLASH END address of bank1 */
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#define FLASH_BANK1_END 0x0801FFFFUL /*!< FLASH END address of bank1 */
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#define SRAM_BASE 0x20000000UL /*!< SRAM base address in the alias region */
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#define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */
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@ -580,11 +585,15 @@ typedef struct
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#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL)
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#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL)
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#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL)
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#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL)
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#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL)
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#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL)
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#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL)
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#define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL)
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#define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL)
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#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL)
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#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL)
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#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400UL)
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#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00UL)
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#define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL)
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@ -594,6 +603,7 @@ typedef struct
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#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00UL)
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#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000UL)
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#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400UL)
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#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800UL)
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#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL)
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#define ADC2_BASE (APB2PERIPH_BASE + 0x00002800UL)
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#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL)
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@ -636,11 +646,15 @@ typedef struct
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#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
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#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
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#define TIM4 ((TIM_TypeDef *)TIM4_BASE)
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#define RTC ((RTC_TypeDef *)RTC_BASE)
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#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
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#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
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#define SPI2 ((SPI_TypeDef *)SPI2_BASE)
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#define USART2 ((USART_TypeDef *)USART2_BASE)
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#define USART3 ((USART_TypeDef *)USART3_BASE)
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#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
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#define I2C2 ((I2C_TypeDef *)I2C2_BASE)
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#define USB ((USB_TypeDef *)USB_BASE)
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#define CAN1 ((CAN_TypeDef *)CAN1_BASE)
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#define BKP ((BKP_TypeDef *)BKP_BASE)
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@ -651,6 +665,7 @@ typedef struct
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#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
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#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
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#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
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#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
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#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
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#define ADC2 ((ADC_TypeDef *)ADC2_BASE)
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#define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
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@ -1185,6 +1200,9 @@ typedef struct
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#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
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#define RCC_APB2RSTR_IOPERST_Pos (6U)
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#define RCC_APB2RSTR_IOPERST_Msk (0x1UL << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
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#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */
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@ -1217,6 +1235,18 @@ typedef struct
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#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
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#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
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#define RCC_APB1RSTR_TIM4RST_Pos (2U)
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#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
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#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */
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#define RCC_APB1RSTR_SPI2RST_Pos (14U)
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#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
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#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */
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#define RCC_APB1RSTR_USART3RST_Pos (18U)
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#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
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#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
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#define RCC_APB1RSTR_I2C2RST_Pos (22U)
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#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
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#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
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#define RCC_APB1RSTR_USBRST_Pos (23U)
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#define RCC_APB1RSTR_USBRST_Msk (0x1UL << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
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@ -1279,6 +1309,9 @@ typedef struct
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#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
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#define RCC_APB2ENR_IOPEEN_Pos (6U)
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#define RCC_APB2ENR_IOPEEN_Msk (0x1UL << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */
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#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */
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@ -1311,6 +1344,18 @@ typedef struct
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#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
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#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
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#define RCC_APB1ENR_TIM4EN_Pos (2U)
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#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
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#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */
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#define RCC_APB1ENR_SPI2EN_Pos (14U)
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#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
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#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */
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#define RCC_APB1ENR_USART3EN_Pos (18U)
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#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
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#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
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#define RCC_APB1ENR_I2C2EN_Pos (22U)
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#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
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#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */
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#define RCC_APB1ENR_USBEN_Pos (23U)
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#define RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
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@ -1999,6 +2044,20 @@ typedef struct
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#define AFIO_MAPR_USART2_REMAP_Msk (0x1UL << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
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#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */
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#define AFIO_MAPR_USART3_REMAP_Pos (4U)
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#define AFIO_MAPR_USART3_REMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */
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#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
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#define AFIO_MAPR_USART3_REMAP_0 (0x1UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */
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#define AFIO_MAPR_USART3_REMAP_1 (0x2UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
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/* USART3_REMAP configuration */
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#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
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#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
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#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
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#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
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#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
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#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */
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#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
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#define AFIO_MAPR_TIM1_REMAP_Pos (6U)
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#define AFIO_MAPR_TIM1_REMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
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@ -2048,6 +2107,9 @@ typedef struct
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#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
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#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
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#define AFIO_MAPR_TIM4_REMAP_Pos (12U)
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#define AFIO_MAPR_TIM4_REMAP_Msk (0x1UL << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */
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#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */
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#define AFIO_MAPR_CAN_REMAP_Pos (13U)
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#define AFIO_MAPR_CAN_REMAP_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */
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@ -9600,12 +9662,18 @@ typedef struct
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#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
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#define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
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#define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
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#define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
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#define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */
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#define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
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#define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U)
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#define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */
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#define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk /*!< Debug CAN1 stopped when Core is halted */
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#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
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#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
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#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
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#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
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#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */
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#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
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/******************************************************************************/
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/* */
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@ -9778,6 +9846,30 @@ typedef struct
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#define FLASH_WRP0_nWRP0_Msk (0xFFUL << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
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#define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
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/****************** Bit definition for FLASH_WRP1 register ******************/
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#define FLASH_WRP1_WRP1_Pos (16U)
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#define FLASH_WRP1_WRP1_Msk (0xFFUL << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
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#define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
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#define FLASH_WRP1_nWRP1_Pos (24U)
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#define FLASH_WRP1_nWRP1_Msk (0xFFUL << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
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#define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
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/****************** Bit definition for FLASH_WRP2 register ******************/
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#define FLASH_WRP2_WRP2_Pos (0U)
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#define FLASH_WRP2_WRP2_Msk (0xFFUL << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */
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#define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
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#define FLASH_WRP2_nWRP2_Pos (8U)
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#define FLASH_WRP2_nWRP2_Msk (0xFFUL << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
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#define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
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/****************** Bit definition for FLASH_WRP3 register ******************/
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#define FLASH_WRP3_WRP3_Pos (16U)
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#define FLASH_WRP3_WRP3_Msk (0xFFUL << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
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#define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
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#define FLASH_WRP3_nWRP3_Pos (24U)
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#define FLASH_WRP3_nWRP3_Msk (0xFFUL << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
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#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
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/**
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@ -9823,7 +9915,8 @@ typedef struct
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#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
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((INSTANCE) == GPIOB) || \
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((INSTANCE) == GPIOC) || \
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((INSTANCE) == GPIOD))
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((INSTANCE) == GPIOD) || \
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((INSTANCE) == GPIOE))
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/**************************** GPIO Alternate Function Instances ***************/
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#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
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@ -9832,7 +9925,8 @@ typedef struct
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#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
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/******************************** I2C Instances *******************************/
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#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
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#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
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((INSTANCE) == I2C2))
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/******************************* SMBUS Instances ******************************/
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#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
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@ -9841,86 +9935,102 @@ typedef struct
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#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
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/******************************** SPI Instances *******************************/
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#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
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#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
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((INSTANCE) == SPI2))
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/****************************** START TIM Instances ***************************/
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/****************************** TIM Instances *********************************/
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#define IS_TIM_INSTANCE(INSTANCE)\
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(((INSTANCE) == TIM1) || \
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((INSTANCE) == TIM2) || \
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((INSTANCE) == TIM3))
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((INSTANCE) == TIM3) || \
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((INSTANCE) == TIM4))
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#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
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#define IS_TIM_CC1_INSTANCE(INSTANCE)\
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(((INSTANCE) == TIM1) || \
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((INSTANCE) == TIM2) || \
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((INSTANCE) == TIM3))
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((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_CC2_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3))
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_CC3_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3))
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_CC4_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3))
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3))
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3))
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3))
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3))
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3))
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3))
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_XOR_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3))
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3))
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3))
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3))
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
|
||||
((INSTANCE) == TIM1)
|
||||
@ -9939,6 +10049,12 @@ typedef struct
|
||||
((CHANNEL) == TIM_CHANNEL_4))) \
|
||||
|| \
|
||||
(((INSTANCE) == TIM3) && \
|
||||
(((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2) || \
|
||||
((CHANNEL) == TIM_CHANNEL_3) || \
|
||||
((CHANNEL) == TIM_CHANNEL_4))) \
|
||||
|| \
|
||||
(((INSTANCE) == TIM4) && \
|
||||
(((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2) || \
|
||||
((CHANNEL) == TIM_CHANNEL_3) || \
|
||||
@ -9953,7 +10069,8 @@ typedef struct
|
||||
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3))
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
|
||||
((INSTANCE) == TIM1)
|
||||
@ -9961,28 +10078,33 @@ typedef struct
|
||||
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3))
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_DMA_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3))
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3))
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
|
||||
((INSTANCE) == TIM1)
|
||||
|
||||
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3))
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3))
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
|
||||
|
||||
@ -9991,39 +10113,48 @@ typedef struct
|
||||
|
||||
/******************** USART Instances : Synchronous mode **********************/
|
||||
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2))
|
||||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == USART3))
|
||||
|
||||
/******************** UART Instances : Asynchronous mode **********************/
|
||||
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2) )
|
||||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == USART3))
|
||||
|
||||
/******************** UART Instances : Half-Duplex mode **********************/
|
||||
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2) )
|
||||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == USART3))
|
||||
|
||||
/******************** UART Instances : LIN mode **********************/
|
||||
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2) )
|
||||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == USART3))
|
||||
|
||||
/****************** UART Instances : Hardware Flow control ********************/
|
||||
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2) )
|
||||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == USART3))
|
||||
|
||||
/********************* UART Instances : Smard card mode ***********************/
|
||||
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2) )
|
||||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == USART3))
|
||||
|
||||
/*********************** UART Instances : IRDA mode ***************************/
|
||||
#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2) )
|
||||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == USART3))
|
||||
|
||||
/***************** UART Instances : Multi-Processor mode **********************/
|
||||
#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2) )
|
||||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == USART3))
|
||||
|
||||
/***************** UART Instances : DMA mode available **********************/
|
||||
#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2))
|
||||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == USART3))
|
||||
|
||||
/****************************** RTC Instances *********************************/
|
||||
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
|
||||
@ -10054,40 +10185,40 @@ typedef struct
|
||||
|
||||
/* Aliases for __IRQn */
|
||||
#define ADC1_IRQn ADC1_2_IRQn
|
||||
#define TIM9_IRQn TIM1_BRK_IRQn
|
||||
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
|
||||
#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
|
||||
#define TIM9_IRQn TIM1_BRK_IRQn
|
||||
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
|
||||
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
|
||||
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
|
||||
#define TIM11_IRQn TIM1_TRG_COM_IRQn
|
||||
#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
|
||||
#define TIM10_IRQn TIM1_UP_IRQn
|
||||
#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
|
||||
#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
|
||||
#define CEC_IRQn USBWakeUp_IRQn
|
||||
#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
|
||||
#define CEC_IRQn USBWakeUp_IRQn
|
||||
#define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
|
||||
#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
|
||||
#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
|
||||
#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
|
||||
#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
|
||||
|
||||
|
||||
/* Aliases for __IRQHandler */
|
||||
#define ADC1_IRQHandler ADC1_2_IRQHandler
|
||||
#define TIM9_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM9_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
|
||||
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
|
||||
#define TIM10_IRQHandler TIM1_UP_IRQHandler
|
||||
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
|
||||
#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
|
||||
#define CEC_IRQHandler USBWakeUp_IRQHandler
|
||||
#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
|
||||
#define CEC_IRQHandler USBWakeUp_IRQHandler
|
||||
#define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
|
||||
#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
|
||||
#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
|
||||
#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
|
||||
#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
|
||||
|
||||
|
||||
/**
|
||||
@ -10103,7 +10234,7 @@ typedef struct
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __STM32F103x6_H */
|
||||
#endif /* __STM32F103xB_H */
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user