feat: v1 done
This commit is contained in:
@ -37,9 +37,9 @@
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"other_text_thickness": 0.15,
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"other_text_upright": false,
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"pads": {
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"drill": 0.8,
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"height": 1.27,
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"width": 2.54
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"drill": 3.2,
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"height": 6.4,
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"width": 6.4
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},
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"silk_line_width": 0.1,
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"silk_text_italic": false,
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@ -58,7 +58,36 @@
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"width": 0.0
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}
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],
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"drc_exclusions": [],
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"drc_exclusions": [
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[
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"clearance|114712500|78250000|57b4eee7-daad-48c9-a9d1-8182b696185a|9c836ad7-72cc-4db6-a9a3-9747dcddbc2b",
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""
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],
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[
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"lib_footprint_mismatch|107000000|37500000|7efa9604-2fc3-4650-928b-0f10d9351b1a|00000000-0000-0000-0000-000000000000",
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""
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],
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[
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"lib_footprint_mismatch|135067500|73600000|6b9f0566-2ddd-4c72-b622-0c68058ef1c2|00000000-0000-0000-0000-000000000000",
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""
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],
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[
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"lib_footprint_mismatch|57000000|97000000|105ada08-9a07-4f34-b129-2b6f2d96024f|00000000-0000-0000-0000-000000000000",
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""
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],
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[
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"lib_footprint_mismatch|62500000|122509500|19763e6d-a497-4ef7-9793-a7ec78a068c7|00000000-0000-0000-0000-000000000000",
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""
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],
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[
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"lib_footprint_mismatch|77993700|64017300|efac08d6-fc9b-4734-bdb4-05f73b2e42cd|00000000-0000-0000-0000-000000000000",
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""
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],
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[
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"lib_footprint_mismatch|81500000|37500000|7cb9a840-9064-4086-a775-fbbc7786457b|00000000-0000-0000-0000-000000000000",
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""
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]
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],
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"meta": {
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"version": 2
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},
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@ -122,7 +151,7 @@
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},
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"rules": {
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"max_error": 0.005,
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"min_clearance": 0.0,
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"min_clearance": 0.0762,
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"min_connection": 0.0,
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"min_copper_edge_clearance": 0.5,
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"min_groove_width": 0.0,
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@ -135,10 +164,10 @@
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"min_text_height": 0.8,
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"min_text_thickness": 0.08,
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"min_through_hole_diameter": 0.3,
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"min_track_width": 0.0,
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"min_via_annular_width": 0.1,
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"min_track_width": 0.0762,
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"min_via_annular_width": 0.15,
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"min_via_diameter": 0.5,
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"solder_mask_to_copper_clearance": 0.0,
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"solder_mask_to_copper_clearance": 0.005,
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"use_height_for_length_calcs": true
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},
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"teardrop_options": [
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@ -229,7 +258,13 @@
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"mfg": "",
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"mpn": ""
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},
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"layer_pairs": [],
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"layer_pairs": [
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{
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"bottomLayer": 2,
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"enabled": true,
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"topLayer": 0
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}
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],
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"layer_presets": [],
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"viewports": []
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},
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@ -238,7 +273,16 @@
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"equivalence_files": []
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},
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"erc": {
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"erc_exclusions": [],
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"erc_exclusions": [
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[
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"lib_symbol_mismatch|355600|1371600|4d1d7321-48a4-47bd-9911-a0129c7c08ec|00000000-0000-0000-0000-000000000000|||",
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"引脚与实际元件不一致"
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],
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[
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"lib_symbol_mismatch|609600|1371600|a508d5b4-8c16-4bfb-9cb2-0305fb53d8fb|00000000-0000-0000-0000-000000000000|||",
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"引脚与实际元件不一致"
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]
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],
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"meta": {
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"version": 0
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},
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@ -442,14 +486,14 @@
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"no_connect_dangling": "warning",
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"pin_not_connected": "error",
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"pin_not_driven": "error",
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"pin_to_pin": "warning",
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"pin_to_pin": "error",
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"power_pin_not_driven": "error",
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"same_local_global_label": "warning",
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"similar_label_and_power": "warning",
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"similar_labels": "warning",
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"similar_power": "warning",
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"simulation_model_issue": "ignore",
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"single_global_label": "ignore",
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"single_global_label": "warning",
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"unannotated": "error",
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"unconnected_wire_endpoint": "warning",
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"unit_value_mismatch": "error",
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@ -458,7 +502,9 @@
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}
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},
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"libraries": {
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"pinned_footprint_libs": [],
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"pinned_footprint_libs": [
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"!Rayine_Components"
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],
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"pinned_symbol_libs": []
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},
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"meta": {
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@ -469,7 +515,7 @@
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"classes": [
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{
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"bus_width": 12,
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"clearance": 0.2,
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"clearance": 0.381,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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@ -480,10 +526,27 @@
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 2147483647,
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.2,
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"track_width": 0.381,
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"via_diameter": 0.6,
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"via_drill": 0.3,
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"wire_width": 6
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},
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{
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"clearance": 1.27,
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"diff_pair_gap": 2.5,
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"name": "AC Power",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 0,
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 1.27
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},
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{
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"clearance": 0.762,
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"name": "Power",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 1,
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.762
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}
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],
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"meta": {
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@ -491,14 +554,35 @@
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},
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"net_colors": null,
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"netclass_assignments": null,
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"netclass_patterns": []
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"netclass_patterns": [
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{
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"netclass": "AC Power",
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"pattern": "L|N"
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},
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{
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"netclass": "AC Power",
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"pattern": "/LOAD*"
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},
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{
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"netclass": "Power",
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"pattern": "5V"
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},
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{
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"netclass": "Power",
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"pattern": "3V3"
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},
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{
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"netclass": "Power",
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"pattern": "GND*"
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}
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]
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},
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"pcbnew": {
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"last_paths": {
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"gencad": "",
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"idf": "",
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"netlist": "",
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"plot": "",
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"plot": "production/",
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"pos_files": "",
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"specctra_dsn": "",
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"step": "",
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@ -620,8 +704,16 @@
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"version": 1
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},
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"net_format_name": "",
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"ngspice": {
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"fix_include_paths": true,
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"meta": {
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"version": 0
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},
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"model_mode": 4,
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"workbook_filename": ""
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},
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"page_layout_descr_file": "",
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"plot_directory": "",
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"plot_directory": "production/",
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"space_save_all_events": true,
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"spice_current_sheet_as_root": false,
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"spice_external_command": "spice \"%I\"",
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