feat(pcb) 交流电部分 PCB Layout

hardware/pcb/HeliosDAONE.kicad_pro

@@ -37,9 +37,9 @@
         "other_text_thickness": 0.15,
         "other_text_upright": false,
         "pads": {
-          "drill": 0.8,
-          "height": 1.27,
-          "width": 2.54
+          "drill": 1.0,
+          "height": 1.7,
+          "width": 1.7
         },
         "silk_line_width": 0.1,
         "silk_text_italic": false,
@@ -51,7 +51,13 @@
           "min_clearance": 0.5
         }
       },
-      "diff_pair_dimensions": [],
+      "diff_pair_dimensions": [
+        {
+          "gap": 0.0,
+          "via_gap": 0.0,
+          "width": 0.0
+        }
+      ],
       "drc_exclusions": [],
       "meta": {
         "version": 2
@@ -179,7 +185,13 @@
           "td_width_to_size_filter_ratio": 0.9
         }
       ],
-      "track_widths": [],
+      "track_widths": [
+        0.0,
+        0.2,
+        1.0,
+        2.54,
+        12.0
+      ],
       "tuning_pattern_settings": {
         "diff_pair_defaults": {
           "corner_radius_percentage": 80,
@@ -206,7 +218,12 @@
           "spacing": 0.6
         }
       },
-      "via_dimensions": [],
+      "via_dimensions": [
+        {
+          "diameter": 0.0,
+          "drill": 0.0
+        }
+      ],
       "zones_allow_external_fillets": false
     },
     "ipc2581": {
@@ -447,10 +464,12 @@
   },
   "libraries": {
     "pinned_footprint_libs": [
-      "RayineComponents"
+      "RayineComponents",
+      "converted"
     ],
     "pinned_symbol_libs": [
-      "RayineComponents"
+      "RayineComponents",
+      "converted"
     ]
   },
   "meta": {
@@ -461,7 +480,7 @@
     "classes": [
       {
         "bus_width": 12,
-        "clearance": 0.2,
+        "clearance": 0.254,
         "diff_pair_gap": 0.25,
         "diff_pair_via_gap": 0.25,
         "diff_pair_width": 0.2,
@@ -472,10 +491,31 @@
         "pcb_color": "rgba(0, 0, 0, 0.000)",
         "priority": 2147483647,
         "schematic_color": "rgba(0, 0, 0, 0.000)",
-        "track_width": 0.2,
+        "track_width": 0.254,
         "via_diameter": 0.6,
         "via_drill": 0.3,
         "wire_width": 6
+      },
+      {
+        "name": "Power In",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "priority": 2,
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 8.0
+      },
+      {
+        "name": "Power Low",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "priority": 0,
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 2.54
+      },
+      {
+        "name": "Power Out",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "priority": 1,
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 6.0
       }
     ],
     "meta": {
@@ -483,7 +523,32 @@
     },
     "net_colors": null,
     "netclass_assignments": null,
-    "netclass_patterns": []
+    "netclass_patterns": [
+      {
+        "netclass": "Power In",
+        "pattern": "L"
+      },
+      {
+        "netclass": "Power In",
+        "pattern": "N"
+      },
+      {
+        "netclass": "Power Out",
+        "pattern": "/L?OUT"
+      },
+      {
+        "netclass": "Power Out",
+        "pattern": "/L?IN"
+      },
+      {
+        "netclass": "Power Low",
+        "pattern": "N_low"
+      },
+      {
+        "netclass": "Power Low",
+        "pattern": "L_low"
+      }
+    ]
   },
   "pcbnew": {
     "last_paths": {