chore: move mcs51 lib to lib
This commit is contained in:
334
.idea/editor.xml
generated
334
.idea/editor.xml
generated
@@ -1,103 +1,6 @@
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@@ -337,7 +240,244 @@
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|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppUninitializedNonStaticDataMember/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRangeBasedForIncompatibleReference/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppZeroValuedExpressionUsedAsNullPointer/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppPossiblyUnintendedObjectSlicing/@EntryIndexRemoved" />
|
||||
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|
||||
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|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppVirtualFunctionInFinalClass/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppMustBePublicVirtualToImplementInterface/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDeclarationSpecifierWithoutDeclarators/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppEmptyDeclaration/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDeclarationHidesLocal/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDeclarationHidesUncapturedLocal/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppMismatchedClassTags/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppUsingResultOfAssignmentAsCondition/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppIntegralToPointerConversion/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppPointerToIntegralConversion/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppIncompatiblePointerConversion/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppPointerConversionDropsQualifiers/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppStringLiteralToCharPointerConversion/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppNonExceptionSafeResourceAcquisition/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppVirtualFunctionCallInsideCtor/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppAbstractVirtualFunctionCallInCtor/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppInvalidLineContinuation/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppPrintfBadFormat/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppPrintfRiskyFormat/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppPrintfMissedArg/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppPrintfExtraArg/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppBoostFormatBadCode/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppBoostFormatLegacyCode/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppBoostFormatMixedArgs/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppBoostFormatTooFewArgs/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppBoostFormatTooManyArgs/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDeprecatedEntity/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppMissingIncludeGuard/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDoxygenSyntaxError/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDoxygenUnresolvedReference/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDoxygenUndocumentedParameter/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDeletingVoidPointer/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppBooleanIncrementExpression/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDeprecatedRegisterStorageClassSpecifier/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppIdenticalOperandsInBinaryExpression/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppEqualOperandsInBinaryExpression/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedefinitionOfDefaultArgumentInOverrideFunction/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppUnnamedNamespaceInHeaderFile/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppParameterNamesMismatch/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDefaultedSpecialMemberFunctionIsImplicitlyDeleted/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppNodiscardFunctionWithoutReturnValue/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantComplexityInComparison/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppAbstractFinalClass/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppSpecialFunctionWithoutNoexceptSpecification/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppUnsignedZeroComparison/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppMultiCharacterLiteral/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppMultiCharacterWideLiteral/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantQualifier/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantAccessSpecifier/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppAccessSpecifierWithNoDeclarations/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantTypenameKeyword/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantTemplateKeyword/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantElseKeyword/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantElseKeywordInsideCompoundStatement/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantControlFlowJump/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantEmptyStatement/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantEmptyDeclaration/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantParentheses/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantLambdaParameterList/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantCastExpression/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppHeaderHasBeenAlreadyIncluded/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppTemplateArgumentsCanBeDeduced/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantTemplateArguments/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppStaticSpecifierOnAnonymousNamespaceMember/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantStaticSpecifierOnMemberAllocationFunction/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantStaticSpecifierOnThreadLocalLocalVariable/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantBaseClassAccessSpecifier/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantInlineSpecifier/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantConstSpecifier/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantBooleanExpressionArgument/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantVoidArgumentList/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantMemberInitializer/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantBaseClassInitializer/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppConstParameterInDeclaration/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppVolatileParameterInDeclaration/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppFinalFunctionInFinalClass/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppFinalNonOverridingVirtualFunction/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantElaboratedTypeSpecifier/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantDereferencingAndTakingAddress/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantConditionalExpression/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppConditionalExpressionCanBeSimplified/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantExportKeyword/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRedundantZeroInitializerInAggregateInitialization/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppUserDefinedLiteralSuffixDoesNotStartWithUnderscore/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppClassIsIncomplete/@EntryIndexRemoved" />
|
||||
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|
||||
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|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDefaultInitializationWithNoUserConstructor/@EntryIndexRemoved" />
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppCoroutineCallResolveError/@EntryIndexRemoved" />
|
||||
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|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppOutParameterMustBeWritten/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppWarningDirective/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppStaticAssertFailure/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppEvaluationFailure/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDeclaratorNeverUsed/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppTypeAliasNeverUsed/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppConceptNeverUsed/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppClassNeverUsed/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppEnumeratorNeverUsed/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppLambdaCaptureNeverUsed/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppLocalVariableWithNonTrivialDtorIsNeverUsed/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppParameterNeverUsed/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppTemplateParameterNeverUsed/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppEntityAssignedButNoRead/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppEntityUsedOnlyInUnevaluatedContext/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppLocalVariableMightNotBeInitialized/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppObjectMemberMightNotBeInitialized/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppSomeObjectMembersMightNotBeInitialized/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDeclaratorUsedBeforeInitialization/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppUnusedIncludeDirective/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppNotAllPathsReturnValue/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CDeclarationWithImplicitIntType/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppFunctionDoesntReturnValue/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppReturnNoValueInNonVoidFunction/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppCVQualifierCanNotBeAppliedToReference/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDereferenceOperatorLimitExceeded/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppForwardEnumDeclarationWithoutUnderlyingType/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppUnmatchedPragmaRegionDirective/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppUnmatchedPragmaEndRegionDirective/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppStaticDataMemberInUnnamedStruct/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDefaultIsUsedAsIdentifier/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppLongFloat/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppMsExtReinterpretCastFromNullptr/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppMsExtBindingRValueToLvalueReference/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppMsExtAddressOfClassRValue/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppMsExtDoubleUserConversionInCopyInit/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppMsExtCopyElisionInCopyInitDeclarator/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppMsExtNotInitializedStaticConstLocalVar/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppRemoveRedundantBraces/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppEnforceIfStatementBraces/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppEnforceForStatementBraces/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppEnforceWhileStatementBraces/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppEnforceDoStatementBraces/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppWrongIncludesOrder/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppWrongSlashesInIncludeDirective/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppEnforceNestedNamespacesStyle/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppEnforceTypeAliasCodeStyle/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppEnforceFunctionDeclarationStyle/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppMemberInitializersOrder/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppEnforceOverridingFunctionStyle/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppEnforceOverridingDestructorStyle/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppUseAuto/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppUseAutoForNumeric/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppEnforceCVQualifiersPlacement/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppEnforceCVQualifiersOrder/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppUnnecessaryWhitespace/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppTabsAreDisallowed/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDFAConstantConditions/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDFANullDereference/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDFANotInitializedField/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDFALoopConditionNotUpdated/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDFADeletedPointer/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDFAMemoryLeak/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDFAInvalidatedMemory/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDFALocalValueEscapesScope/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDFALocalValueEscapesFunction/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDFAConstantParameter/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDFAConstantFunctionResult/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDFAArrayIndexOutOfBounds/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDFAUnreachableCode/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDFAUnreachableFunctionCall/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDFAEndlessLoop/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDFAInfiniteRecursion/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDFAUnusedValue/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDFAUnreadVariable/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppDFATimeOver/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CppInconsistentNaming/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=StringLiteralTypo/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=CommentTypo/@EntryIndexRemoved" />
|
||||
<option name="/Default/CodeInspection/Highlighting/InspectionSeverities/=IdentifierTypo/@EntryIndexRemoved" />
|
||||
</component>
|
||||
</project>
|
||||
2
.idea/vcs.xml
generated
2
.idea/vcs.xml
generated
@@ -1,6 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<project version="4">
|
||||
<component name="VcsDirectoryMappings">
|
||||
<mapping directory="$PROJECT_DIR$" vcs="Git" />
|
||||
<mapping directory="" vcs="Git" />
|
||||
</component>
|
||||
</project>
|
||||
180
lib/mcs51/8051.h
Normal file
180
lib/mcs51/8051.h
Normal file
@@ -0,0 +1,180 @@
|
||||
/*-------------------------------------------------------------------------
|
||||
8051.h: Register Declarations for the Intel 8051 Processor
|
||||
|
||||
Copyright (C) 2000, Bela Torok / bela.torok@kssg.ch
|
||||
|
||||
This library is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the
|
||||
Free Software Foundation; either version 2, or (at your option) any
|
||||
later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this library; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
|
||||
MA 02110-1301, USA.
|
||||
|
||||
As a special exception, if you link this library with other files,
|
||||
some of which are compiled with SDCC, to produce an executable,
|
||||
this library does not by itself cause the resulting executable to
|
||||
be covered by the GNU General Public License. This exception does
|
||||
not however invalidate any other reasons why the executable file
|
||||
might be covered by the GNU General Public License.
|
||||
-------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef REG8051_H
|
||||
#define REG8051_H
|
||||
|
||||
#include "lint.h"
|
||||
/* BYTE Register */
|
||||
__sfr __at (0x80) P0 ;
|
||||
__sfr __at (0x81) SP ;
|
||||
__sfr __at (0x82) DPL ;
|
||||
__sfr __at (0x83) DPH ;
|
||||
__sfr __at (0x87) PCON ;
|
||||
__sfr __at (0x88) TCON ;
|
||||
__sfr __at (0x89) TMOD ;
|
||||
__sfr __at (0x8A) TL0 ;
|
||||
__sfr __at (0x8B) TL1 ;
|
||||
__sfr __at (0x8C) TH0 ;
|
||||
__sfr __at (0x8D) TH1 ;
|
||||
__sfr __at (0x90) P1 ;
|
||||
__sfr __at (0x98) SCON ;
|
||||
__sfr __at (0x99) SBUF ;
|
||||
__sfr __at (0xA0) P2 ;
|
||||
__sfr __at (0xA8) IE ;
|
||||
__sfr __at (0xB0) P3 ;
|
||||
__sfr __at (0xB8) IP ;
|
||||
__sfr __at (0xD0) PSW ;
|
||||
__sfr __at (0xE0) ACC ;
|
||||
__sfr __at (0xF0) B ;
|
||||
|
||||
|
||||
/* BIT Register */
|
||||
/* P0 */
|
||||
__sbit __at (0x80) P0_0 ;
|
||||
__sbit __at (0x81) P0_1 ;
|
||||
__sbit __at (0x82) P0_2 ;
|
||||
__sbit __at (0x83) P0_3 ;
|
||||
__sbit __at (0x84) P0_4 ;
|
||||
__sbit __at (0x85) P0_5 ;
|
||||
__sbit __at (0x86) P0_6 ;
|
||||
__sbit __at (0x87) P0_7 ;
|
||||
|
||||
/* TCON */
|
||||
__sbit __at (0x88) IT0 ;
|
||||
__sbit __at (0x89) IE0 ;
|
||||
__sbit __at (0x8A) IT1 ;
|
||||
__sbit __at (0x8B) IE1 ;
|
||||
__sbit __at (0x8C) TR0 ;
|
||||
__sbit __at (0x8D) TF0 ;
|
||||
__sbit __at (0x8E) TR1 ;
|
||||
__sbit __at (0x8F) TF1 ;
|
||||
|
||||
/* P1 */
|
||||
__sbit __at (0x90) P1_0 ;
|
||||
__sbit __at (0x91) P1_1 ;
|
||||
__sbit __at (0x92) P1_2 ;
|
||||
__sbit __at (0x93) P1_3 ;
|
||||
__sbit __at (0x94) P1_4 ;
|
||||
__sbit __at (0x95) P1_5 ;
|
||||
__sbit __at (0x96) P1_6 ;
|
||||
__sbit __at (0x97) P1_7 ;
|
||||
|
||||
/* SCON */
|
||||
__sbit __at (0x98) RI ;
|
||||
__sbit __at (0x99) TI ;
|
||||
__sbit __at (0x9A) RB8 ;
|
||||
__sbit __at (0x9B) TB8 ;
|
||||
__sbit __at (0x9C) REN ;
|
||||
__sbit __at (0x9D) SM2 ;
|
||||
__sbit __at (0x9E) SM1 ;
|
||||
__sbit __at (0x9F) SM0 ;
|
||||
|
||||
/* P2 */
|
||||
__sbit __at (0xA0) P2_0 ;
|
||||
__sbit __at (0xA1) P2_1 ;
|
||||
__sbit __at (0xA2) P2_2 ;
|
||||
__sbit __at (0xA3) P2_3 ;
|
||||
__sbit __at (0xA4) P2_4 ;
|
||||
__sbit __at (0xA5) P2_5 ;
|
||||
__sbit __at (0xA6) P2_6 ;
|
||||
__sbit __at (0xA7) P2_7 ;
|
||||
|
||||
/* IE */
|
||||
__sbit __at (0xA8) EX0 ;
|
||||
__sbit __at (0xA9) ET0 ;
|
||||
__sbit __at (0xAA) EX1 ;
|
||||
__sbit __at (0xAB) ET1 ;
|
||||
__sbit __at (0xAC) ES ;
|
||||
__sbit __at (0xAF) EA ;
|
||||
|
||||
/* P3 */
|
||||
__sbit __at (0xB0) P3_0 ;
|
||||
__sbit __at (0xB1) P3_1 ;
|
||||
__sbit __at (0xB2) P3_2 ;
|
||||
__sbit __at (0xB3) P3_3 ;
|
||||
__sbit __at (0xB4) P3_4 ;
|
||||
__sbit __at (0xB5) P3_5 ;
|
||||
__sbit __at (0xB6) P3_6 ;
|
||||
__sbit __at (0xB7) P3_7 ;
|
||||
|
||||
__sbit __at (0xB0) RXD ;
|
||||
__sbit __at (0xB1) TXD ;
|
||||
__sbit __at (0xB2) INT0 ;
|
||||
__sbit __at (0xB3) INT1 ;
|
||||
__sbit __at (0xB4) T0 ;
|
||||
__sbit __at (0xB5) T1 ;
|
||||
__sbit __at (0xB6) WR ;
|
||||
__sbit __at (0xB7) RD ;
|
||||
|
||||
/* IP */
|
||||
__sbit __at (0xB8) PX0 ;
|
||||
__sbit __at (0xB9) PT0 ;
|
||||
__sbit __at (0xBA) PX1 ;
|
||||
__sbit __at (0xBB) PT1 ;
|
||||
__sbit __at (0xBC) PS ;
|
||||
|
||||
/* PSW */
|
||||
__sbit __at (0xD0) P ;
|
||||
__sbit __at (0xD1) F1 ;
|
||||
__sbit __at (0xD2) OV ;
|
||||
__sbit __at (0xD3) RS0 ;
|
||||
__sbit __at (0xD4) RS1 ;
|
||||
__sbit __at (0xD5) F0 ;
|
||||
__sbit __at (0xD6) AC ;
|
||||
__sbit __at (0xD7) CY ;
|
||||
|
||||
/* BIT definitions for bits that are not directly accessible */
|
||||
/* PCON bits */
|
||||
#define IDL 0x01
|
||||
#define PD 0x02
|
||||
#define GF0 0x04
|
||||
#define GF1 0x08
|
||||
#define SMOD 0x80
|
||||
|
||||
/* TMOD bits */
|
||||
#define T0_M0 0x01
|
||||
#define T0_M1 0x02
|
||||
#define T0_CT 0x04
|
||||
#define T0_GATE 0x08
|
||||
#define T1_M0 0x10
|
||||
#define T1_M1 0x20
|
||||
#define T1_CT 0x40
|
||||
#define T1_GATE 0x80
|
||||
|
||||
#define T0_MASK 0x0F
|
||||
#define T1_MASK 0xF0
|
||||
|
||||
/* Interrupt numbers: address = (number * 8) + 3 */
|
||||
#define IE0_VECTOR 0 /* 0x03 external interrupt 0 */
|
||||
#define TF0_VECTOR 1 /* 0x0b timer 0 */
|
||||
#define IE1_VECTOR 2 /* 0x13 external interrupt 1 */
|
||||
#define TF1_VECTOR 3 /* 0x1b timer 1 */
|
||||
#define SI0_VECTOR 4 /* 0x23 serial port 0 */
|
||||
|
||||
#endif
|
||||
74
lib/mcs51/8052.h
Normal file
74
lib/mcs51/8052.h
Normal file
@@ -0,0 +1,74 @@
|
||||
/*-------------------------------------------------------------------------
|
||||
8052.h: Register Declarations for the Intel 8052 Processor
|
||||
|
||||
Copyright (C) 2000, Bela Torok / bela.torok@kssg.ch
|
||||
|
||||
This library is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the
|
||||
Free Software Foundation; either version 2, or (at your option) any
|
||||
later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this library; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
|
||||
MA 02110-1301, USA.
|
||||
|
||||
As a special exception, if you link this library with other files,
|
||||
some of which are compiled with SDCC, to produce an executable,
|
||||
this library does not by itself cause the resulting executable to
|
||||
be covered by the GNU General Public License. This exception does
|
||||
not however invalidate any other reasons why the executable file
|
||||
might be covered by the GNU General Public License.
|
||||
-------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef REG8052_H
|
||||
#define REG8052_H
|
||||
|
||||
#include <8051.h> /* load definitions for the 8051 core */
|
||||
|
||||
#ifdef REG8051_H
|
||||
#undef REG8051_H
|
||||
#endif
|
||||
|
||||
/* define 8052 specific registers only */
|
||||
|
||||
/* T2CON */
|
||||
__sfr __at (0xC8) T2CON ;
|
||||
|
||||
/* RCAP2 L & H */
|
||||
__sfr __at (0xCA) RCAP2L ;
|
||||
__sfr __at (0xCB) RCAP2H ;
|
||||
__sfr __at (0xCC) TL2 ;
|
||||
__sfr __at (0xCD) TH2 ;
|
||||
|
||||
/* IE */
|
||||
__sbit __at (0xAD) ET2 ; /* Enable timer2 interrupt */
|
||||
|
||||
/* IP */
|
||||
__sbit __at (0xBD) PT2 ; /* T2 interrupt priority bit */
|
||||
|
||||
/* T2CON bits */
|
||||
__sbit __at (0xC8) T2CON_0 ;
|
||||
__sbit __at (0xC9) T2CON_1 ;
|
||||
__sbit __at (0xCA) T2CON_2 ;
|
||||
__sbit __at (0xCB) T2CON_3 ;
|
||||
__sbit __at (0xCC) T2CON_4 ;
|
||||
__sbit __at (0xCD) T2CON_5 ;
|
||||
__sbit __at (0xCE) T2CON_6 ;
|
||||
__sbit __at (0xCF) T2CON_7 ;
|
||||
|
||||
__sbit __at (0xC8) CP_RL2 ;
|
||||
__sbit __at (0xC9) C_T2 ;
|
||||
__sbit __at (0xCA) TR2 ;
|
||||
__sbit __at (0xCB) EXEN2 ;
|
||||
__sbit __at (0xCC) TCLK ;
|
||||
__sbit __at (0xCD) RCLK ;
|
||||
__sbit __at (0xCE) EXF2 ;
|
||||
__sbit __at (0xCF) TF2 ;
|
||||
|
||||
#endif
|
||||
384
lib/mcs51/ADuC84x.h
Normal file
384
lib/mcs51/ADuC84x.h
Normal file
@@ -0,0 +1,384 @@
|
||||
/*-------------------------------------------------------------------------
|
||||
ADuC84x.h: Register Declarations for Analog Devices
|
||||
ADuC841/ADuC842/ADuC843 (Based on datasheet Rev 0, 11/2003 )
|
||||
|
||||
Copyright (C) 2007, Jesus Calvino-Fraga / jesusc at ece.ubc.ca
|
||||
|
||||
This library is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the
|
||||
Free Software Foundation; either version 2, or (at your option) any
|
||||
later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this library; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
|
||||
MA 02110-1301, USA.
|
||||
|
||||
As a special exception, if you link this library with other files,
|
||||
some of which are compiled with SDCC, to produce an executable,
|
||||
this library does not by itself cause the resulting executable to
|
||||
be covered by the GNU General Public License. This exception does
|
||||
not however invalidate any other reasons why the executable file
|
||||
might be covered by the GNU General Public License.
|
||||
-------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef REG_ADUC84X_H
|
||||
#define REG_ADUC84X_H
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
SFR(CFG841, 0xAF); // ADuC841 Configuration SFR.
|
||||
SFR(CFG842, 0xAF); // ADuC842/ADuC843 Configuration SFR.
|
||||
//For the two SFRs above these are the bits. Warning: some are different for
|
||||
//the ADuC841 and ADuC842/ADuC843. Check the datasheet!
|
||||
#define EPM2 0x10 // Flash/EE Controller and PWM Clock Frequency Configuration Bit 2.
|
||||
#define EPM1 0x08 // Flash/EE Controller and PWM Clock Frequency Configuration Bit 1.
|
||||
#define EPM0 0x04 // Flash/EE Controller and PWM Clock Frequency Configuration Bit 0.
|
||||
#define EXSP 0x80 // Extended SP Enable.
|
||||
#define PWPO 0x40 // PWM Pin Out Selection.
|
||||
#define DBUF 0x20 // DAC Output Buffer.
|
||||
#define EXTCLK 0x10 // Set by the user to 1 to select an external clock input on P3.4.
|
||||
#define MSPI 0x02 // Set to 1 by the user to move the SPI functionality of.
|
||||
#define XRAMEN 0x01 // XRAM Enable Bit.
|
||||
|
||||
SFR(SP, 0x81); // Stack Pointer.
|
||||
SFR(SPH, 0xB7); // Stack pointer high.
|
||||
|
||||
SFR(DPL, 0x82); // Data Pointer Low.
|
||||
SFR(DPH, 0x83); // Data Pointer High.
|
||||
SFR(DPP, 0x84); // Data Pointer Page Byte.
|
||||
SFR(DPCON, 0xA7); // Data Pointer Control SFR.
|
||||
|
||||
SFR(PCON, 0x87); // Power Control.
|
||||
#define SMOD 0x80 //Double UART Baud Rate.
|
||||
#define SERIPD 0x40 //I2C/SPI Power-Down Interrupt Enable.
|
||||
#define INT0PD 0x20 //INT0 Power-Down Interrupt Enable.
|
||||
#define ALEOFF 0x10 //Disable ALE Output.
|
||||
#define GF1 0x08 //General-Purpose Flag Bit.
|
||||
#define GF0 0x04 //General-Purpose Flag Bit.
|
||||
#define PD 0x02 //Power-Down Mode Enable.
|
||||
#define IDL 0x01 //Idle Mode Enable.
|
||||
|
||||
SFR(TCON, 0x88); // Timer/Counter Control.
|
||||
SBIT(TF1, 0x88, 7); // Timer 1 overflow flag.
|
||||
SBIT(TR1, 0x88, 6); // Timer 1 run control flag.
|
||||
SBIT(TF0, 0x88, 5); // Timer 0 overflow flag.
|
||||
SBIT(TR0, 0x88, 4); // Timer 0 run control flag.
|
||||
SBIT(IE1, 0x88, 3); // Interrupt 1 flag.
|
||||
SBIT(IT1, 0x88, 2); // Interrupt 1 type control bit.
|
||||
SBIT(IE0, 0x88, 1); // Interrupt 0 flag.
|
||||
SBIT(IT0, 0x88, 0); // Interrupt 0 type control bit.
|
||||
|
||||
SFR(TMOD, 0x89); // Timer/Counter Mode Control.
|
||||
#define GATE1 0x80 // External enable for timer 1.
|
||||
#define C_T1 0x40 // Timer or counter select for timer 1.
|
||||
#define M1_1 0x20 // Operation mode bit 1 for timer 1.
|
||||
#define M0_1 0x10 // Operation mode bit 0 for timer 1.
|
||||
#define GATE0 0x08 // External enable for timer 0.
|
||||
#define C_T0 0x04 // Timer or counter select for timer 0.
|
||||
#define M1_0 0x02 // Operation mode bit 1 for timer 0.
|
||||
#define M0_0 0x01 // Operation mode bit 0 for timer 0.
|
||||
|
||||
SFR(TL0, 0x8A); // Timer 0 LSB.
|
||||
SFR(TL1, 0x8B); // Timer 1 LSB.
|
||||
SFR(TH0, 0x8C); // Timer 0 MSB.
|
||||
SFR(TH1, 0x8D); // Timer 1 MSB.
|
||||
|
||||
SFR(P0, 0x80); // Port 0
|
||||
SBIT(P0_0, 0x80, 0); // Port 0 bit 0.
|
||||
SBIT(P0_1, 0x80, 1); // Port 0 bit 1.
|
||||
SBIT(P0_2, 0x80, 2); // Port 0 bit 2.
|
||||
SBIT(P0_3, 0x80, 3); // Port 0 bit 3.
|
||||
SBIT(P0_4, 0x80, 4); // Port 0 bit 4.
|
||||
SBIT(P0_5, 0x80, 5); // Port 0 bit 5.
|
||||
SBIT(P0_6, 0x80, 6); // Port 0 bit 6.
|
||||
SBIT(P0_7, 0x80, 7); // Port 0 bit 7.
|
||||
|
||||
SFR(P1, 0x90); // Port 1
|
||||
SBIT(P1_0, 0x90, 0); // Port 1 bit 0.
|
||||
SBIT(P1_1, 0x90, 1); // Port 1 bit 1.
|
||||
SBIT(P1_2, 0x90, 2); // Port 1 bit 2.
|
||||
SBIT(P1_3, 0x90, 3); // Port 1 bit 3.
|
||||
SBIT(P1_4, 0x90, 4); // Port 1 bit 4.
|
||||
SBIT(P1_5, 0x90, 5); // Port 1 bit 5.
|
||||
SBIT(P1_6, 0x90, 6); // Port 1 bit 6.
|
||||
SBIT(P1_7, 0x90, 7); // Port 1 bit 7.
|
||||
// Alternate names
|
||||
SBIT(T2EX, 0x90, 1); //Capture/reload trigger for Counter 2.
|
||||
SBIT(T2, 0x90, 0); //Input to Timer/Counter 2.
|
||||
|
||||
SFR(P2, 0xA0); // Port 2
|
||||
SBIT(P2_0, 0xA0, 0); // Port 2 bit 0.
|
||||
SBIT(P2_1, 0xA0, 1); // Port 2 bit 1.
|
||||
SBIT(P2_2, 0xA0, 2); // Port 2 bit 2.
|
||||
SBIT(P2_3, 0xA0, 3); // Port 2 bit 3.
|
||||
SBIT(P2_4, 0xA0, 4); // Port 2 bit 4.
|
||||
SBIT(P2_5, 0xA0, 5); // Port 2 bit 5.
|
||||
SBIT(P2_6, 0xA0, 6); // Port 2 bit 6.
|
||||
SBIT(P2_7, 0xA0, 7); // Port 2 bit 7.
|
||||
|
||||
SFR(P3, 0xB0); // Port 3
|
||||
SBIT(P3_0, 0xB0, 0); // Port 3 bit 0.
|
||||
SBIT(P3_1, 0xB0, 1); // Port 3 bit 1.
|
||||
SBIT(P3_2, 0xB0, 2); // Port 3 bit 2.
|
||||
SBIT(P3_3, 0xB0, 3); // Port 3 bit 3.
|
||||
SBIT(P3_4, 0xB0, 4); // Port 3 bit 4.
|
||||
SBIT(P3_5, 0xB0, 5); // Port 3 bit 5.
|
||||
SBIT(P3_6, 0xB0, 6); // Port 3 bit 6.
|
||||
SBIT(P3_7, 0xB0, 7); // Port 3 bit 7.
|
||||
// Alternate names.
|
||||
SBIT(RXD, 0xB0, 0);
|
||||
SBIT(TXD, 0xB0, 1);
|
||||
SBIT(INT0, 0xB0, 2);
|
||||
SBIT(INT1, 0xB0, 3);
|
||||
SBIT(T0, 0xB0, 4);
|
||||
SBIT(T1, 0xB0, 5);
|
||||
SBIT(WR, 0xB0, 6);
|
||||
SBIT(RD, 0xB0, 7);
|
||||
|
||||
SFR(I2CADD, 0x9B); // I2C Address Register 1.
|
||||
SFR(I2CADD1, 0x91); // I2C Address Register 2.
|
||||
SFR(I2CADD2, 0x92); // I2C Address Register 3.
|
||||
SFR(I2CADD3, 0x93); // I2C Address Register 4.
|
||||
SFR(I2CDAT, 0x9A); // I2C Data Register.
|
||||
|
||||
SFR(SCON, 0x98); // Serial Port Control.
|
||||
SBIT(SM0, 0x98, 7); // Serial Port Mode Bit 0.
|
||||
SBIT(SM1, 0x98, 6); // Serial Port Mode Bit 1.
|
||||
SBIT(SM2, 0x98, 5); // Serial Port Mode Bit 2.
|
||||
SBIT(REN, 0x98, 4); // Enables serial reception.
|
||||
SBIT(TB8, 0x98, 3); // The 9th data bit that will be transmitted in Modes 2 and 3.
|
||||
SBIT(RB8, 0x98, 2); // In Modes 2 and 3, the 9th data bit that was received.
|
||||
SBIT(TI, 0x98, 1); // Transmit interrupt flag.
|
||||
SBIT(RI, 0x98, 0); // Receive interrupt flag.
|
||||
|
||||
SFR(SBUF, 0x99); // Serial Data Buffer.
|
||||
|
||||
//For these two, you may want to check page 68 of the datasheet...
|
||||
SFR(T3FD, 0x9D); // Fractional divider ratio.
|
||||
SFR(T3CON, 0x9E); // T3CON is the baud rate control SFR, allowing Timer 3 to be
|
||||
// used to set up the UART baud rate, and setting up the binary
|
||||
// divider (DIV).
|
||||
#define T3BAUDEN 0x80 // T3 UART BAUD Enable.
|
||||
#define DIV2 0x04 // Binary Divider Factor bit 3.
|
||||
#define DIV1 0x02 // Binary Divider Factor bit 2.
|
||||
#define DIV0 0x01 // Binary Divider Factor bit 1.
|
||||
|
||||
SFR(TIMECON, 0xA1); // TIC Control Register.
|
||||
#define TFH 0x40 // Twenty-Four Hour Select Bit.
|
||||
#define ITS1 0x20 // Interval Timebase Selection Bit 1.
|
||||
#define ITS0 0x10 // Interval Timebase Selection Bit 1.
|
||||
#define STI 0x08 // Single Time Interval Bit.
|
||||
#define TII 0x04 // TIC Interrupt Bit.
|
||||
#define TIEN 0x02 // Time Interval Enable Bit.
|
||||
#define TCEN 0x01 // Time Clock Enable Bit.
|
||||
|
||||
SFR(HTHSEC, 0xA2); // Hundredths Seconds Time Register.
|
||||
SFR(SEC, 0xA3); // Seconds Time Register.
|
||||
SFR(MIN, 0xA4); // Minutes Time Register.
|
||||
SFR(HOUR, 0xA5); // Hours Time Register.
|
||||
SFR(INTVAL, 0xA6); // User Time Interval Select Register.
|
||||
|
||||
SFR(IE, 0xA8); // Interrupt Enable.
|
||||
SBIT(EA, 0xA8, 7); // Global Interrupt Enable.
|
||||
SBIT(EADC, 0xA8, 6); // ADC Interrupt Enable.
|
||||
SBIT(ET2, 0xA8, 5); // Timer 2 Interrupt Enable.
|
||||
SBIT(ES, 0xA8, 4); // Serial Interrupt Enable.
|
||||
SBIT(ET1, 0xA8, 3); // Timer 1 Interrupt Enable.
|
||||
SBIT(EX1, 0xA8, 2); // External 1 Interrupt Enable.
|
||||
SBIT(ET0, 0xA8, 1); // Timer 0 Interrupt Enable.
|
||||
SBIT(EX0, 0xA8, 0); // External 0 Interrupt Enable.
|
||||
|
||||
SFR(IEIP2, 0xA9); // Secondary Interrupt Enable Register
|
||||
#define PTI 0x40 // Priority for time interval interrupt.
|
||||
#define PPSM 0x20 // Priority for power supply monitor interrupt.
|
||||
#define PSI2 0x10 // Priority for SPI/I2C interrupt. Same name as bit in IP???
|
||||
#define ETI 0x04 // Enable time interval counter interrupts.
|
||||
#define EPSMI 0x02 // Enable power supply monitor interrupts.
|
||||
#define ESI 0x01 // Enable SPI or I2C serial port interrupts.
|
||||
|
||||
SFR(PWMCON, 0xAE); //PWM control.
|
||||
#define SNGL 0x80 // Turns off PMW output at P2.6 or P3.4.
|
||||
#define MD2 0x40 // PWM Mode Bit 2.
|
||||
#define MD1 0x20 // PWM Mode Bit 2.
|
||||
#define MD0 0x10 // PWM Mode Bit 2.
|
||||
#define CDIV1 0x08 // PWM Clock Divider bit 1.
|
||||
#define CDIV0 0x04 // PWM Clock Divider bit 1.
|
||||
#define CSEL1 0x02 // PWM Clock Select bit 1. (Typo in datasheet???)
|
||||
#define CSEL0 0x01 // PWM Clock Select bit 0.
|
||||
|
||||
SFR(PWM0L, 0xB1); // PWM 0 duty cycle low.
|
||||
SFR(PWM0H, 0xB2); // PWM 0 duty cycle high.
|
||||
SFR(PWM1L, 0xB3); // PWM 1 duty cycle low.
|
||||
SFR(PWM1H, 0xB4); // PWM 1 duty cycle high.
|
||||
|
||||
SFR(IP, 0xB8); // Interrupt Priority Reg.
|
||||
SBIT(PSI, 0xB8, 7); // Priority for SPI/I2C interrupt.
|
||||
SBIT(PADC, 0xB8, 6); // ADC interrupt priority bit.
|
||||
SBIT(PT2, 0xB8, 5); // Timer 2 interrupt priority bit.
|
||||
SBIT(PS, 0xB8, 4); // Serial Port interrupt priority bit.
|
||||
SBIT(PT1, 0xB8, 3); // Timer 1 interrupt priority bit.
|
||||
SBIT(PX1, 0xB8, 2); // External interrupt 1 priority bit.
|
||||
SBIT(PT0, 0xB8, 1); // Timer 0 interrupt priority bit.
|
||||
SBIT(PX0, 0xB8, 0); // External interrupt 0 priority bit.
|
||||
|
||||
SFR(ECON, 0xB9); // Flash/EE Memory Control SFR.
|
||||
SFR(EDATA1, 0xBC); // EE page data byte 1.
|
||||
SFR(EDATA2, 0xBD); // EE page data byte 2.
|
||||
SFR(EDATA3, 0xBE); // EE page data byte 3.
|
||||
SFR(EDATA4, 0xBF); // EE page data byte 4.
|
||||
SFR(EADRL, 0xC6); // EE address low.
|
||||
SFR(EADRH, 0xC7); // EE address high.
|
||||
|
||||
SFR(WDCON, 0xC0); //Watchdog Timer Control Register.
|
||||
SBIT(PRE3, 0xc0, 7); // Timeout period bit 4.
|
||||
SBIT(PRE2, 0xc0, 6); // Timeout period bit 3.
|
||||
SBIT(PRE1, 0xc0, 5); // Timeout period bit 2.
|
||||
SBIT(PRE0, 0xc0, 4); // Timeout period bit 1.
|
||||
SBIT(WDIR, 0xc0, 3); // Watchdog Interrupt Response Enable Bit.
|
||||
SBIT(WDS, 0xc0, 2); // Watchdog Status Bit.
|
||||
SBIT(WDE, 0xc0, 1); // Watchdog Enable Bit.
|
||||
SBIT(WDWR, 0xc0, 0); // Watchdog Write Enable Bit.
|
||||
|
||||
SFR(CHIPID, 0xC2); // System Self-Identification? WARNING: No description in the datasheet.
|
||||
|
||||
SFR(T2CON, 0xC8); // Timer / Counter 2 Control.
|
||||
SBIT(TF2, 0xC8, 7); // Timer 2 overflow flag.
|
||||
SBIT(EXF2, 0xC8, 6); // Timer 2 external flag.
|
||||
SBIT(RCLK, 0xC8, 5); // Receive clock flag.
|
||||
SBIT(TCLK, 0xC8, 4); // Transmit clock flag.
|
||||
SBIT(EXEN2, 0xC8, 3); // Timer 2 external enable flag.
|
||||
SBIT(TR2, 0xC8, 2); // Start/stop control for timer 2.
|
||||
SBIT(CNT2, 0xC8, 1); // Timer or coutner select.
|
||||
SBIT(CAP2, 0xC8, 0); // Capture/reload flag.
|
||||
|
||||
SFR(RCAP2L, 0xCA); // Timer 2 Capture LSB.
|
||||
SFR(RCAP2H, 0xCB); // Timer 2 Capture MSB.
|
||||
SFR(TL2, 0xCC); // Timer 2 LSB.
|
||||
SFR(TH2, 0xCD); // Timer 2 MSB.
|
||||
|
||||
SFR(PSW, 0xD0); // Program Status Word.
|
||||
SBIT(CY, 0xD0, 7); // Carry Flag.
|
||||
SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag.
|
||||
SBIT(F0, 0xD0, 5); // User-Defined Flag.
|
||||
SBIT(RS1, 0xD0, 4); // Register Bank Select 1.
|
||||
SBIT(RS0, 0xD0, 3); // Register Bank Select 0.
|
||||
SBIT(OV, 0xD0, 2); // Overflow Flag.
|
||||
SBIT(F1, 0xD0, 1); // User-Defined Flag.
|
||||
SBIT(P, 0xD0, 0); // Parity Flag.
|
||||
|
||||
SFR(DMAL, 0xD2); // DMA mode address pointer low.
|
||||
SFR(DMAH, 0xD3); // DMA mode address pointer high.
|
||||
SFR(DMAP, 0xD4); // DMA mode address pointer page. (?)
|
||||
SFR(PLLCON, 0xD7); // PLL Control Register.
|
||||
|
||||
SFR(PSMCON, 0xDF); // Power supply monitor.
|
||||
#define CMPD 0x40 // DVDD Comparator Bit.
|
||||
#define PSMI 0x20 // Power Supply Monitor Interrupt Bit.
|
||||
#define TPD1 0x10 // DVDD Trip Point Selection Bit 2.
|
||||
#define TPD0 0x08 // DVDD Trip Point Selection Bit 1.
|
||||
#define PSMEN 0x01 // Power Supply Monitor Enable Bit.
|
||||
|
||||
SFR(ACC, 0xE0); // Accumulator
|
||||
SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0.
|
||||
SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1.
|
||||
SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2.
|
||||
SBIT(ACC_3, 0xE0, 3); // Accumulator bit 3.
|
||||
SBIT(ACC_4, 0xE0, 4); // Accumulator bit 4.
|
||||
SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5.
|
||||
SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6.
|
||||
SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7.
|
||||
|
||||
SFR(I2CCON, 0xE8); // I2C Control Register
|
||||
// Master mode
|
||||
SBIT(MDO, 0xE8, 7); // I2C Software Master Data Output Bit.
|
||||
SBIT(MDE, 0xE8, 6); // I2C Software Master Data Output Enable Bit.
|
||||
SBIT(MCO, 0xE8, 5); // I2C Software Master Clock Output Bit.
|
||||
SBIT(MDI, 0xE8, 4); // I2C Software Master Data Input Bit.
|
||||
// Slave mode
|
||||
SBIT(I2CSI, 0xE8, 7); // I2C Stop Interrupt Enable Bit.
|
||||
SBIT(I2CGC, 0xE8, 6); // I2C General Call Status Bit.
|
||||
SBIT(I2CID1, 0xE8, 5); // I2C Interrupt Decode Bit 2.
|
||||
SBIT(I2CID0, 0xE8, 4); // I2C Interrupt Decode Bit 1.
|
||||
SBIT(I2CM, 0xE8, 3); // I2C Master/Slave Mode Bit.
|
||||
SBIT(I2CRS, 0xE8, 2); // I2C Reset Bit.
|
||||
SBIT(I2CTX, 0xE8, 1); // I2C Direction Transfer Bit.
|
||||
SBIT(I2CI, 0xE8, 0); // I2C Interrupt Bit.
|
||||
|
||||
SFR(B, 0xF0); // B Register
|
||||
SBIT(B_0, 0xF0, 0); // Register B bit 0.
|
||||
SBIT(B_1, 0xF0, 1); // Register B bit 1.
|
||||
SBIT(B_2, 0xF0, 2); // Register B bit 2.
|
||||
SBIT(B_3, 0xF0, 3); // Register B bit 3.
|
||||
SBIT(B_4, 0xF0, 4); // Register B bit 4.
|
||||
SBIT(B_5, 0xF0, 5); // Register B bit 5.
|
||||
SBIT(B_6, 0xF0, 6); // Register B bit 6.
|
||||
SBIT(B_7, 0xF0, 7); // Register B bit 7.
|
||||
|
||||
SFR(ADCCON1, 0xEF); //ADC Control SFR 1
|
||||
//WARNING: bit 7 is named MD1 in the datasheet, but that name is already used.
|
||||
#define MD 0x80 // The mode bit selects the active operating mode of the ADC.
|
||||
#define EXT_REF 0x40 // Set by the user to select an external reference.
|
||||
#define CK1 0x20 // The ADC clock divide bit 1.
|
||||
#define CK0 0x10 // The ADC clock divide bit 0.
|
||||
#define AQ1 0x08 // ADC acquisition select bit 1.
|
||||
#define AQ0 0x04 // ADC acquisition select bit 0.
|
||||
#define T2C 0x02 // The Timer 2 conversion bit.
|
||||
#define EXC 0x01 // The external trigger enable bit.
|
||||
|
||||
SFR(ADCCON2, 0xD8); // ADC Control SFR 2.
|
||||
SBIT(ADCI, 0xD8, 7); // ADC Interrupt Bit.
|
||||
SBIT(DMA, 0xD8, 6); // DMA Mode Enable Bit.
|
||||
SBIT(CCONV, 0xD8, 5); // Continuous Conversion Bit.
|
||||
SBIT(SCONV, 0xD8, 4); // Single Conversion Bit.
|
||||
SBIT(CS3, 0xD8, 3); // Channel Selection Bit 4.
|
||||
SBIT(CS2, 0xD8, 2); // Channel Selection Bit 3.
|
||||
SBIT(CS1, 0xD8, 1); // Channel Selection Bit 2.
|
||||
SBIT(CS0, 0xD8, 0); // Channel Selection Bit 1.
|
||||
|
||||
SFR(ADCCON3, 0xF5); //ADC Control SFR 3
|
||||
#define BUSY 0x80 // ADC Busy Status Bit.
|
||||
#define AVGS1 0x20 // Number of Average Selection Bit 2.
|
||||
#define AVGS0 0x10 // Number of Average Selection Bit 1.
|
||||
#define TYPICAL 0x02 // Calibration Type Select Bit.
|
||||
#define SCAL 0x01 // Start Calibration Cycle Bit.
|
||||
|
||||
SFR(ADCDATAL, 0xD9); // ADC Result byte low.
|
||||
SFR(ADCDATAH, 0xDA); // ADC Result byte high. WARNING: bits 4 to 7 are the ADC channel!
|
||||
SFR(ADCOFSL, 0xF1); // Offset calibration coefficient byte (low).
|
||||
SFR(ADCOFSH, 0xF2); // Offset calibration coefficient byte (high).
|
||||
SFR(ADCGAINL, 0xF3); // Gain calibration coefficient byte (low).
|
||||
SFR(ADCGAINH, 0xF4); // Gain calibration coefficient byte (high).
|
||||
|
||||
SFR(SPIDAT, 0xF7); // SPI Data Register.
|
||||
|
||||
SFR(SPICON, 0xF8); // SPI Control Register.
|
||||
SBIT(ISPI, 0xF8, 7); // SPI Interrupt Bit.
|
||||
SBIT(WCOL, 0xF8, 6); // Write Collision Error Bit.
|
||||
SBIT(SPE, 0xF8, 5); // SPI Interface Enable Bit.
|
||||
SBIT(SPIM, 0xF8, 4); // SPI Master/Slave Mode Select Bit.
|
||||
SBIT(CPOL, 0xF8, 3); // Clock Polarity Select Bit.
|
||||
SBIT(CPHA, 0xF8, 2); // Clock Phase Select Bit.
|
||||
SBIT(SPR1, 0xF8, 1); // SPI Bit Rate Select Bit 2.
|
||||
SBIT(SPR0, 0xF8, 0); // SPI Bit Rate Select Bit 1.
|
||||
|
||||
SFR(DAC0L, 0xF9); // DAC0 Data Low Byte.
|
||||
SFR(DAC0H, 0xFA); // DAC0 Data High Byte.
|
||||
SFR(DAC1L, 0xFB); // DAC1 Data Low Byte.
|
||||
SFR(DAC1H, 0xFC); // DAC1 Data High Byte.
|
||||
SFR(DACCON, 0xFD); // DAC Control Register.
|
||||
#define MODE 0x80 // 8/12 bit selection.
|
||||
#define RNG1 0x40 // DAC1 Range Select Bit.
|
||||
#define RNG0 0x20 // DAC0 Range Select Bit.
|
||||
#define CLR1 0x10 // DAC1 Clear Bit.
|
||||
#define CLR0 0x08 // DAC0 Clear Bit.
|
||||
#define SYNC 0x04 // DAC0/1 Update Synchronization Bit.
|
||||
#define PD1 0x02 // DAC1 Power-Down Bit.
|
||||
#define PD0 0x01 // DAC0 Power-Down Bit.
|
||||
|
||||
#endif //REG_ADUC84X_H
|
||||
258
lib/mcs51/AT89C513xA.h
Normal file
258
lib/mcs51/AT89C513xA.h
Normal file
@@ -0,0 +1,258 @@
|
||||
/*-------------------------------------------------------------------------
|
||||
Register Declarations for the Atmel AT89C513xA Processor Range
|
||||
|
||||
Copyright (C) 2010 - Anirban Brahmachari, a.brahmachari@gmail.com
|
||||
|
||||
This library is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the
|
||||
Free Software Foundation; either version 2, or (at your option) any
|
||||
later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this library; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
|
||||
MA 02110-1301, USA.
|
||||
|
||||
As a special exception, if you link this library with other files,
|
||||
some of which are compiled with SDCC, to produce an executable,
|
||||
this library does not by itself cause the resulting executable to
|
||||
be covered by the GNU General Public License. This exception does
|
||||
not however invalidate any other reasons why the executable file
|
||||
might be covered by the GNU General Public License.
|
||||
-------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef AT89C5131AUM_H
|
||||
#define AT89C5131AUM_H
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
SFR(P0, 0x80); // Port 0
|
||||
SBIT(P0_0, 0x80, 0); // Port 0 bit 0
|
||||
SBIT(P0_1, 0x80, 1); // Port 0 bit 1
|
||||
SBIT(P0_2, 0x80, 2); // Port 0 bit 2
|
||||
SBIT(P0_3, 0x80, 3); // Port 0 bit 3
|
||||
SBIT(P0_4, 0x80, 4); // Port 0 bit 4
|
||||
SBIT(P0_5, 0x80, 5); // Port 0 bit 5
|
||||
SBIT(P0_6, 0x80, 6); // Port 0 bit 6
|
||||
SBIT(P0_7, 0x80, 7); // Port 0 bit 7
|
||||
SFR(SP, 0x81); // Stack Pointer ; LSB of SPX
|
||||
SFR(DPL, 0x82); // Data Pointer Low Byte
|
||||
SFR(DPH, 0x83); // Data Pointer High Byte
|
||||
SFR(PCON, 0x87); // Power Mode Control
|
||||
SFR(TCON, 0x88); // Timer Control
|
||||
SBIT(IT0, 0x88, 0); // Ext. Interrupt 0 Type Select
|
||||
SBIT(IE0, 0x88, 1); // Ext. Interrupt 0 Flag
|
||||
SBIT(IT1, 0x88, 2); // Ext. Interrupt 1 Type Select
|
||||
SBIT(IE1, 0x88, 3); // Ext. Interrupt 1 Flag
|
||||
SBIT(TR0, 0x88, 4); // Timer 0 Run Control
|
||||
SBIT(TF0, 0x88, 5); // Timer 0 Overflow Flag
|
||||
SBIT(TR1, 0x88, 6); // Timer 1 Run Control
|
||||
SBIT(TF1, 0x88, 7); // Timer 1 Overflow Flag
|
||||
SFR(TMOD, 0x89); // Timer Mode
|
||||
SFR16E(TMR0, 0x8C8A); // Timer/Counter 0 Word
|
||||
SFR(TL0, 0x8A); // Timer/Counter 0 Low Byte
|
||||
SFR(TH0, 0x8C); // Timer/Counter 0 High Byte
|
||||
SFR16E(TMR1, 0x8D8B); // Timer/Counter 1 Word
|
||||
SFR(TL1, 0x8B); // Timer/Counter 1 Low Byte
|
||||
SFR(TH1, 0x8D); // Timer/Counter 1 High Byte
|
||||
SFR(AUXR, 0x8E); // Auxiliary Register
|
||||
SFR(CKCON0, 0x8F); // Clock Control 0
|
||||
SFR(P1, 0x90); // Port 1
|
||||
SBIT(P1_0, 0x90, 0); // Port 1 bit 0
|
||||
SBIT(P1_1, 0x90, 1); // Port 1 bit 1
|
||||
SBIT(P1_2, 0x90, 2); // Port 1 bit 2
|
||||
SBIT(P1_3, 0x90, 3); // Port 1 bit 3
|
||||
SBIT(P1_4, 0x90, 4); // Port 1 bit 4
|
||||
SBIT(P1_5, 0x90, 5); // Port 1 bit 5
|
||||
SBIT(P1_6, 0x90, 6); // Port 1 bit 6
|
||||
SBIT(P1_7, 0x90, 7); // Port 1 bit 7
|
||||
SFR(SSCON, 0x93); // Synchronous Serial Control
|
||||
SFR(SSCS, 0x94); // Synchronous Serial Control-Status
|
||||
SFR(SSDAT, 0x95); // Synchronous Serial Data
|
||||
SFR(SSADR, 0x96); // Synchronous Serial Address
|
||||
SFR(SCON, 0x98); // Serial Port 0 Control
|
||||
SBIT(RI, 0x98, 0); // Receive Interrupt Flag
|
||||
SBIT(TI, 0x98, 1); // Transmit Interrupt Flag
|
||||
SBIT(RB8, 0x98, 2); // Ninth Receive Bit
|
||||
SBIT(TB8, 0x98, 3); // Ninth Transmission Bit
|
||||
SBIT(REN, 0x98, 4); // Receive Enable
|
||||
SBIT(SM2, 0x98, 5); // Multiprocessor Communication Enable
|
||||
SBIT(SM1, 0x98, 6); // Serial Port Mode 1
|
||||
SBIT(SM0, 0x98, 7); // Serial Port Mode 0
|
||||
SBIT(FE, 0x98, 7); // Framing Error
|
||||
SFR(SBUF, 0x99); // Serial Port Data Buffer
|
||||
SFR(BRL, 0x9A); // Baud Rate Reload
|
||||
SFR(BDRCON, 0x9B); // Baud Rate Control
|
||||
SFR(KBLS, 0x9C); // Keyboard Level Selector Register
|
||||
SFR(KBE, 0x9D); // Keyboard Input Enable Register
|
||||
SFR(KBF, 0x9E); // Keyboard Flag Register
|
||||
SFR(P2, 0xA0); // Port 2
|
||||
SBIT(P2_0, 0xA0, 0); // Port 2 bit 0
|
||||
SBIT(P2_1, 0xA0, 1); // Port 2 bit 1
|
||||
SBIT(P2_2, 0xA0, 2); // Port 2 bit 2
|
||||
SBIT(P2_3, 0xA0, 3); // Port 2 bit 3
|
||||
SBIT(P2_4, 0xA0, 4); // Port 2 bit 4
|
||||
SBIT(P2_5, 0xA0, 5); // Port 2 bit 5
|
||||
SBIT(P2_6, 0xA0, 6); // Port 2 bit 6
|
||||
SBIT(P2_7, 0xA0, 7); // Port 2 bit 7
|
||||
SFR(AUXR1, 0xA2); // Auxiliary Register 1
|
||||
SFR(PLLCON, 0xA3); // PLL Control
|
||||
SFR(PLLDIV, 0xA4); // PLL Divider
|
||||
SFR(WDTRST, 0xA6); // Watchdog Timer Reset
|
||||
SFR(WDTPRG, 0xA7); // Watchdog Timer Program
|
||||
SFR(IE, 0xA8); // Interrupt Enable (traditional 8051 name)
|
||||
SFR(IEN0, 0xA8); // Interrupt Enable Control 0
|
||||
SBIT(EX0, 0xA8, 0); // Enable External Interrupt 0
|
||||
SBIT(ET0, 0xA8, 1); // Enable Timer 0 Interrupt
|
||||
SBIT(EX1, 0xA8, 2); // Enable External Interrupt 1
|
||||
SBIT(ET1, 0xA8, 3); // Enable Timer 1 Interrupt
|
||||
SBIT(ES, 0xA8, 4); // Enable Serial Port Interrupt
|
||||
SBIT(ET2, 0xA8, 5); // Enable Timer 2 Interrupt
|
||||
SBIT(EC, 0xA8, 6); // Enable PCA Interrupt
|
||||
SBIT(EA, 0xA8, 7); // Global Interrupt Enable
|
||||
SFR(SADDR, 0xA9); // Slave Address
|
||||
SFR(CKCON1, 0xAF); // Clock Control 1
|
||||
SFR(P3, 0xB0); // Port 3
|
||||
SBIT(P3_0, 0xB0, 0); // Port 3 bit 0
|
||||
SBIT(P3_1, 0xB0, 1); // Port 3 bit 1
|
||||
SBIT(P3_2, 0xB0, 2); // Port 3 bit 2
|
||||
SBIT(P3_3, 0xB0, 3); // Port 3 bit 3
|
||||
SBIT(P3_4, 0xB0, 4); // Port 3 bit 4
|
||||
SBIT(P3_5, 0xB0, 5); // Port 3 bit 5
|
||||
SBIT(P3_6, 0xB0, 6); // Port 3 bit 6
|
||||
SBIT(P3_7, 0xB0, 7); // Port 3 bit 7
|
||||
SFR(IEN1, 0xB1); // Interrupt Enable Control 1
|
||||
SFR(IPL1, 0xB2); // Interrupt Priority Control Low 1
|
||||
SFR(IPH1, 0xB3); // Interrupt Priority Control High 1
|
||||
SFR(IPH0, 0xB7); // Interrupt Priority Control High 0
|
||||
SFR(IPL0, 0xB8); // Interrupt Priority Control Low 0
|
||||
SBIT(PX0L, 0xB8, 0); // External interrupt 0 Priority bit
|
||||
SBIT(PT0L, 0xB8, 1); // Timer 0 overflow interrupt Priority bit
|
||||
SBIT(PX1L, 0xB8, 2); // External interrupt 1 Priority bit
|
||||
SBIT(PT1L, 0xB8, 3); // Timer 1 overflow interrupt Priority bit
|
||||
SBIT(PSL, 0xB8, 4); // Serial port Priority bit
|
||||
SBIT(PT2L, 0xB8, 5); // Timer 2 overflow interrupt Priority bit
|
||||
SBIT(PPCL, 0xB8, 6); // PCA interrupt Priority bit
|
||||
SFR(SADEN, 0xB9); // Slave Address Mask
|
||||
SFR16E(UFNUM, 0xBBBA); // USB Frame Number Word
|
||||
SFR(UFNUML, 0xBA); // USB Frame Number Low
|
||||
SFR(UFNUMH, 0xBB); // USB Frame Number High
|
||||
SFR(USBCON, 0xBC); // USB Global Control
|
||||
SFR(USBINT, 0xBD); // USB Global Interrupt
|
||||
SFR(USBIEN, 0xBE); // USB Global Interrupt Enable
|
||||
SFR(P4, 0xC0); // Port 4
|
||||
SBIT(P4_0, 0xC0, 0); // Port 4 bit 0
|
||||
SBIT(P4_1, 0xC0, 1); // Port 4 bit 1
|
||||
SFR(UEPIEN, 0xC2); // USB Endpoint Interrupt Enable
|
||||
SFR(SPCON, 0xC3); // Serial Peripheral Control
|
||||
SFR(SPSTA, 0xC4); // Serial Peripheral Status-Control
|
||||
SFR(SPDAT, 0xC5); // Serial Peripheral Data
|
||||
SFR(USBADDR, 0xC6); // USB Address
|
||||
SFR(UEPNUM, 0xC7); // USB Endpoint Number
|
||||
SFR(T2CON, 0xC8); // Timer 2 Control
|
||||
SBIT(CP_RL2, 0xC8, 0); // Timer 2 Capture/Reload bit
|
||||
SBIT(C_T2, 0xC8, 1); // Timer/Counter 2 select bit
|
||||
SBIT(TR2, 0xC8, 2); // Timer 2 Run control bit
|
||||
SBIT(EXEN2, 0xC8, 3); // Timer 2 External Enable bit
|
||||
SBIT(TCLK, 0xC8, 4); // Transmit Clock bit
|
||||
SBIT(RCLK, 0xC8, 5); // Receive Clock bit
|
||||
SBIT(EXF2, 0xC8, 6); // Timer 2 External Flag
|
||||
SBIT(TF2, 0xC8, 7); // Timer 2 overflow Flag
|
||||
SFR(T2MOD, 0xC9); // Timer 2 Mode
|
||||
SFR16E(RCAP2, 0xCBCA); // Timer/Counter 2 Reload/Capture Word
|
||||
SFR(RCAP2L, 0xCA); // Timer/Counter 2 Reload/Capture Low byte
|
||||
SFR(RCAP2H, 0xCB); // Timer/Counter 2 Reload/Capture High byte
|
||||
SFR16E(TMR2, 0xCDCC); // Timer/Counter 2 Word
|
||||
SFR(TL2, 0xCC); // Timer/Counter 2 Low Byte
|
||||
SFR(TH2, 0xCD); // Timer/Counter 2 High Byte
|
||||
SFR(UEPSTAX, 0xCE); // USB Endpoint X Status
|
||||
SFR(UEPDATX, 0xCF); // USB Endpoint X FIFO Data
|
||||
SFR(PSW, 0xD0); // Program Status Word
|
||||
SBIT(P, 0xD0, 0); // Parity Flag
|
||||
SBIT(F1, 0xD0, 1); // User-Defined Flag
|
||||
SBIT(OV, 0xD0, 2); // Overflow Flag
|
||||
SBIT(RS0, 0xD0, 3); // Register Bank Select 0
|
||||
SBIT(RS1, 0xD0, 4); // Register Bank Select 1
|
||||
SBIT(F0, 0xD0, 5); // User-Defined Flag
|
||||
SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag
|
||||
SBIT(CY, 0xD0, 7); // Carry Flag
|
||||
SFR(FCON, 0xD1); // Flash Control
|
||||
SFR(EECON, 0xD2); // EEPROM Contol
|
||||
SFR(UEPCONX, 0xD4); // USB Endpoint X Control
|
||||
SFR(UEPRST, 0xD5); // USB Endpoint Reset
|
||||
SFR(CCON, 0xD8); // PCA Timer/Counter Control
|
||||
SBIT(CCF0, 0xD8,0); // PCA Module 0 interrupt flag
|
||||
SBIT(CCF1, 0xD8,1); // PCA Module 1 interrupt flag
|
||||
SBIT(CCF2, 0xD8,2); // PCA Module 2 interrupt flag
|
||||
SBIT(CCF3, 0xD8,3); // PCA Module 3 interrupt flag
|
||||
SBIT(CCF4, 0xD8,4); // PCA Module 4 interrupt flag
|
||||
SBIT(CR, 0xD8,6); // PCA Counter Run control bit
|
||||
SBIT(CF, 0xD8,7); // PCA Counter Overflow flag
|
||||
SFR(CMOD, 0xD9); // PCA Timer/Counter Mode
|
||||
SFR(CCAPM0, 0xDA); // PCA Timer/Counter 0 Mode
|
||||
SFR(CCAPM1, 0xDB); // PCA Timer/Counter 1 Mode
|
||||
SFR(CCAPM2, 0xDC); // PCA Timer/Counter 2 Mode
|
||||
SFR(CCAPM3, 0xDD); // PCA Timer/Counter 3 Mode
|
||||
SFR(CCAPM4, 0xDE); // PCA Timer/Counter 4 Mode
|
||||
SFR(ACC, 0xE0); // Accumulator
|
||||
SFR16E(UBYCTX, 0xE3E2); // USB Byte Counter Word
|
||||
SFR(UBYCTLX, 0xE2); // USB Byte Counter Low
|
||||
SFR(UBYCTHX, 0xE3); // USB Byte Counter High
|
||||
SFR16E(PCA, 0xF9E9); // PCA Timer/Counter Word
|
||||
SFR(CL, 0xE9); // PCA Timer/Counter Low byte
|
||||
SFR(CH, 0xF9); // PCA Timer/Counter High byte
|
||||
SFR16E(CCAP0, 0xFAEA); // PCA Compare Capture Module 0 Word
|
||||
SFR(CCAP0L, 0xEA); // PCA Compare Capture Module 0 Low byte
|
||||
SFR(CCAP0H, 0xFA); // PCA Compare Capture Module 0 High byte
|
||||
SFR16E(CCAP1, 0xFBEB); // PCA Compare Capture Module 1 Word
|
||||
SFR(CCAP1L, 0xEB); // PCA Compare Capture Module 1 Low byte
|
||||
SFR(CCAP1H, 0xFB); // PCA Compare Capture Module 1 High byte
|
||||
SFR16E(CCAP2, 0xFCEC); // PCA Compare Capture Module 2 Word
|
||||
SFR(CCAP2L, 0xEC); // PCA Compare Capture Module 2 Low byte
|
||||
SFR(CCAP2H, 0xFC); // PCA Compare Capture Module 2 High byte
|
||||
SFR16E(CCAP3, 0xFDED); // PCA Compare Capture Module 3 Word
|
||||
SFR(CCAP3L, 0xED); // PCA Compare Capture Module 3 Low byte
|
||||
SFR(CCAP3H, 0xFD); // PCA Compare Capture Module 3 High byte
|
||||
SFR16E(CCAP4, 0xFEEE); // PCA Compare Capture Module 4 Word
|
||||
SFR(CCAP4L, 0xEE); // PCA Compare Capture Module 4 Low byte
|
||||
SFR(CCAP4H, 0xFE); // PCA Compare Capture Module 4 High byte
|
||||
SFR(B, 0xF0); // B Register
|
||||
SFR(LEDCON, 0xF1); // LED Control
|
||||
SFR(UEPINT, 0xF8); // USB Endpoint Interrupt
|
||||
SBIT(EP0INT, 0xF8,0); // Endpoint 0 Interrupt
|
||||
SBIT(EP1INT, 0xF8,1); // Endpoint 1 Interrupt
|
||||
SBIT(EP2INT, 0xF8,2); // Endpoint 2 Interrupt
|
||||
SBIT(EP3INT, 0xF8,3); // Endpoint 3 Interrupt
|
||||
SBIT(EP4INT, 0xF8,4); // Endpoint 4 Interrupt
|
||||
SBIT(EP5INT, 0xF8,5); // Endpoint 5 Interrupt
|
||||
SBIT(EP6INT, 0xF8,6); // Endpoint 6 Interrupt
|
||||
|
||||
/* Predefined SFR Bit Masks */
|
||||
|
||||
#define PCON_IDLE 0x01 /* PCON */
|
||||
#define PCON_STOP 0x02 /* PCON */
|
||||
|
||||
/* Interrupts */
|
||||
#define INT_RESET 0 // Reset
|
||||
#define INT_EXT0 1 // External Interrupt 0
|
||||
#define INT_TIMER0 2 // Timer0 Overflow
|
||||
#define INT_EXT1 3 // External Interrupt 1
|
||||
#define INT_TIMER1 4 // Timer1 Overflow
|
||||
#define INT_UART0 5 // Serial Port 0
|
||||
#define INT_TIMER2 6 // Timer2 Overflow
|
||||
#define INT_PCA 7 // Programmable Counter Array
|
||||
#define INT_KEYBOARD 8 // Keyboard on P1
|
||||
#define INT_TWI 9 // Two Wire Interface
|
||||
#define INT_SPI 10 // Serial Peripheral Interface
|
||||
// 11 Reserved
|
||||
// 12 Reserved
|
||||
// 13 Reserved
|
||||
#define INT_USB 14 // USB events
|
||||
// 15 Reserved
|
||||
|
||||
#endif
|
||||
313
lib/mcs51/C8051F000.h
Normal file
313
lib/mcs51/C8051F000.h
Normal file
@@ -0,0 +1,313 @@
|
||||
/*---------------------------------------------------------------------------
|
||||
C8051F000.h - Register Declarations for the Cygnal/SiLabs C8051F000-F017
|
||||
Processor Range
|
||||
|
||||
Copyright (C) 2003, Maarten Brock, sourceforge.brock@dse.nl
|
||||
|
||||
This library is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the
|
||||
Free Software Foundation; either version 2, or (at your option) any
|
||||
later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this library; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
|
||||
MA 02110-1301, USA.
|
||||
|
||||
As a special exception, if you link this library with other files,
|
||||
some of which are compiled with SDCC, to produce an executable,
|
||||
this library does not by itself cause the resulting executable to
|
||||
be covered by the GNU General Public License. This exception does
|
||||
not however invalidate any other reasons why the executable file
|
||||
might be covered by the GNU General Public License.
|
||||
-------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef C8051F000_H
|
||||
#define C8051F000_H
|
||||
|
||||
|
||||
/* BYTE Registers */
|
||||
__sfr __at (0x80) P0 ; /* PORT 0 */
|
||||
__sfr __at (0x81) SP ; /* STACK POINTER */
|
||||
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
|
||||
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
|
||||
__sfr __at (0x87) PCON ; /* POWER CONTROL */
|
||||
__sfr __at (0x88) TCON ; /* TIMER CONTROL */
|
||||
__sfr __at (0x89) TMOD ; /* TIMER MODE */
|
||||
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
|
||||
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
|
||||
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
|
||||
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
|
||||
__sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
|
||||
__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
|
||||
__sfr __at (0x90) P1 ; /* PORT 1 */
|
||||
__sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */
|
||||
__sfr __at (0x92) TMR3RLL ; /* TIMER 3 RELOAD REGISTER - LOW BYTE */
|
||||
__sfr __at (0x93) TMR3RLH ; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */
|
||||
__sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */
|
||||
__sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */
|
||||
__sfr __at (0x98) SCON ; /* SERIAL PORT CONTROL */
|
||||
__sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
|
||||
__sfr __at (0x9A) SPI0CFG ; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */
|
||||
__sfr __at (0x9B) SPI0DAT ; /* SERIAL PERIPHERAL INTERFACE 0 DATA */
|
||||
__sfr __at (0x9D) SPI0CKR ; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */
|
||||
__sfr __at (0x9E) CPT0CN ; /* COMPARATOR 0 CONTROL */
|
||||
__sfr __at (0x9F) CPT1CN ; /* COMPARATOR 1 CONTROL */
|
||||
__sfr __at (0xA0) P2 ; /* PORT 2 */
|
||||
__sfr __at (0xA4) PRT0CF ; /* PORT 0 CONFIGURATION */
|
||||
__sfr __at (0xA5) PRT1CF ; /* PORT 1 CONFIGURATION */
|
||||
__sfr __at (0xA6) PRT2CF ; /* PORT 2 CONFIGURATION */
|
||||
__sfr __at (0xA7) PRT3CF ; /* PORT 3 CONFIGURATION */
|
||||
__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
|
||||
__sfr __at (0xAD) PRT1IF ; /* PORT 1 EXTERNAL INTERRUPT FLAGS */
|
||||
__sfr __at (0xAF) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
|
||||
__sfr __at (0xAF) _XPAGE ; /* XDATA/PDATA PAGE */
|
||||
__sfr __at (0xB0) P3 ; /* PORT 3 */
|
||||
__sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
|
||||
__sfr __at (0xB7) FLACL ; /* FLASH ACESS LIMIT */
|
||||
__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
|
||||
__sfr __at (0xBA) AMX0CF ; /* ADC 0 MUX CONFIGURATION */
|
||||
__sfr __at (0xBB) AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
|
||||
__sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */
|
||||
__sfr __at (0xBE) ADC0L ; /* ADC 0 DATA - LOW BYTE */
|
||||
__sfr __at (0xBF) ADC0H ; /* ADC 0 DATA - HIGH BYTE */
|
||||
__sfr __at (0xC0) SMB0CN ; /* SMBUS 0 CONTROL */
|
||||
__sfr __at (0xC1) SMB0STA ; /* SMBUS 0 STATUS */
|
||||
__sfr __at (0xC2) SMB0DAT ; /* SMBUS 0 DATA */
|
||||
__sfr __at (0xC3) SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
|
||||
__sfr __at (0xC4) ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
|
||||
__sfr __at (0xC5) ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xC6) ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
|
||||
__sfr __at (0xC7) ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
|
||||
__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
|
||||
__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
|
||||
__sfr __at (0xCF) SMB0CR ; /* SMBUS 0 CLOCK RATE */
|
||||
__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
|
||||
__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
|
||||
__sfr __at (0xD2) DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
|
||||
__sfr __at (0xD3) DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xD4) DAC0CN ; /* DAC 0 CONTROL */
|
||||
__sfr __at (0xD5) DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
|
||||
__sfr __at (0xD6) DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xD7) DAC1CN ; /* DAC 1 CONTROL */
|
||||
__sfr __at (0xD8) PCA0CN ; /* PCA 0 COUNTER CONTROL */
|
||||
__sfr __at (0xD9) PCA0MD ; /* PCA 0 COUNTER MODE */
|
||||
__sfr __at (0xDA) PCA0CPM0 ; /* CONTROL REGISTER FOR PCA 0 MODULE 0 */
|
||||
__sfr __at (0xDB) PCA0CPM1 ; /* CONTROL REGISTER FOR PCA 0 MODULE 1 */
|
||||
__sfr __at (0xDC) PCA0CPM2 ; /* CONTROL REGISTER FOR PCA 0 MODULE 2 */
|
||||
__sfr __at (0xDD) PCA0CPM3 ; /* CONTROL REGISTER FOR PCA 0 MODULE 3 */
|
||||
__sfr __at (0xDE) PCA0CPM4 ; /* CONTROL REGISTER FOR PCA 0 MODULE 4 */
|
||||
__sfr __at (0xE0) ACC ; /* ACCUMULATOR */
|
||||
__sfr __at (0xE1) XBR0 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 */
|
||||
__sfr __at (0xE2) XBR1 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 */
|
||||
__sfr __at (0xE3) XBR2 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 2 */
|
||||
__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
|
||||
__sfr __at (0xE7) EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
|
||||
__sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */
|
||||
__sfr __at (0xE9) PCA0L ; /* PCA 0 TIMER - LOW BYTE */
|
||||
__sfr __at (0xEA) PCA0CPL0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */
|
||||
__sfr __at (0xEB) PCA0CPL1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */
|
||||
__sfr __at (0xEC) PCA0CPL2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */
|
||||
__sfr __at (0xED) PCA0CPL3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */
|
||||
__sfr __at (0xEE) PCA0CPL4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */
|
||||
__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
|
||||
__sfr __at (0xF0) B ; /* B REGISTER */
|
||||
__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
|
||||
__sfr __at (0xF7) EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
|
||||
__sfr __at (0xF8) SPI0CN ; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL */
|
||||
__sfr __at (0xF9) PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
|
||||
__sfr __at (0xFA) PCA0CPH0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */
|
||||
__sfr __at (0xFB) PCA0CPH1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */
|
||||
__sfr __at (0xFC) PCA0CPH2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */
|
||||
__sfr __at (0xFD) PCA0CPH3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */
|
||||
__sfr __at (0xFE) PCA0CPH4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */
|
||||
__sfr __at (0xFF) WDTCN ; /* WATCHDOG TIMER CONTROL */
|
||||
|
||||
|
||||
/* WORD/DWORD Registers */
|
||||
|
||||
__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
|
||||
__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
|
||||
__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
|
||||
__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
|
||||
__sfr16 __at (0x9594) TMR3 ; /* TIMER 3 COUNTER */
|
||||
__sfr16 __at (0x9392) TMR3RL ; /* TIMER 3 CAPTURE REGISTER WORD */
|
||||
__sfr16 __at (0xBFBE) ADC0 ; /* ADC 0 DATA WORD */
|
||||
__sfr16 __at (0xC5C4) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */
|
||||
__sfr16 __at (0xC7C6) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */
|
||||
__sfr16 __at (0xD3D2) DAC0 ; /* DAC 0 REGISTER WORD */
|
||||
__sfr16 __at (0xD6D5) DAC1 ; /* DAC 1 REGISTER WORD */
|
||||
__sfr16 __at (0xF9E9) PCA0 ; /* PCA COUNTER */
|
||||
__sfr16 __at (0xFAEA) PCA0CP0 ; /* PCA CAPTURE 0 WORD */
|
||||
__sfr16 __at (0xFBEB) PCA0CP1 ; /* PCA CAPTURE 1 WORD */
|
||||
__sfr16 __at (0xFCEC) PCA0CP2 ; /* PCA CAPTURE 2 WORD */
|
||||
__sfr16 __at (0xFDED) PCA0CP3 ; /* PCA CAPTURE 3 WORD */
|
||||
__sfr16 __at (0xFEEE) PCA0CP4 ; /* PCA CAPTURE 4 WORD */
|
||||
|
||||
|
||||
/* BIT Registers */
|
||||
|
||||
/* P0 0x80 */
|
||||
__sbit __at (0x87) P0_7 ;
|
||||
__sbit __at (0x86) P0_6 ;
|
||||
__sbit __at (0x85) P0_5 ;
|
||||
__sbit __at (0x84) P0_4 ;
|
||||
__sbit __at (0x83) P0_3 ;
|
||||
__sbit __at (0x82) P0_2 ;
|
||||
__sbit __at (0x81) P0_1 ;
|
||||
__sbit __at (0x80) P0_0 ;
|
||||
|
||||
/* TCON 0x88 */
|
||||
__sbit __at (0x8F) TF1 ; /* TIMER 1 OVERFLOW FLAG */
|
||||
__sbit __at (0x8E) TR1 ; /* TIMER 1 ON/OFF CONTROL */
|
||||
__sbit __at (0x8D) TF0 ; /* TIMER 0 OVERFLOW FLAG */
|
||||
__sbit __at (0x8C) TR0 ; /* TIMER 0 ON/OFF CONTROL */
|
||||
__sbit __at (0x8B) IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
|
||||
__sbit __at (0x8A) IT1 ; /* EXT. INTERRUPT 1 TYPE */
|
||||
__sbit __at (0x89) IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
|
||||
__sbit __at (0x88) IT0 ; /* EXT. INTERRUPT 0 TYPE */
|
||||
|
||||
/* P1 0x90 */
|
||||
__sbit __at (0x97) P1_7 ;
|
||||
__sbit __at (0x96) P1_6 ;
|
||||
__sbit __at (0x95) P1_5 ;
|
||||
__sbit __at (0x94) P1_4 ;
|
||||
__sbit __at (0x93) P1_3 ;
|
||||
__sbit __at (0x92) P1_2 ;
|
||||
__sbit __at (0x91) P1_1 ;
|
||||
__sbit __at (0x90) P1_0 ;
|
||||
|
||||
/* SCON 0x98 */
|
||||
__sbit __at (0x9F) SM0 ; /* SERIAL MODE CONTROL BIT 0 */
|
||||
__sbit __at (0x9E) SM1 ; /* SERIAL MODE CONTROL BIT 1 */
|
||||
__sbit __at (0x9D) SM2 ; /* MULTIPROCESSOR COMMUNICATION ENABLE */
|
||||
__sbit __at (0x9C) REN ; /* RECEIVE ENABLE */
|
||||
__sbit __at (0x9B) TB8 ; /* TRANSMIT BIT 8 */
|
||||
__sbit __at (0x9A) RB8 ; /* RECEIVE BIT 8 */
|
||||
__sbit __at (0x99) TI ; /* TRANSMIT INTERRUPT FLAG */
|
||||
__sbit __at (0x98) RI ; /* RECEIVE INTERRUPT FLAG */
|
||||
|
||||
/* P2 0xA0 */
|
||||
__sbit __at (0xA7) P2_7 ;
|
||||
__sbit __at (0xA6) P2_6 ;
|
||||
__sbit __at (0xA5) P2_5 ;
|
||||
__sbit __at (0xA4) P2_4 ;
|
||||
__sbit __at (0xA3) P2_3 ;
|
||||
__sbit __at (0xA2) P2_2 ;
|
||||
__sbit __at (0xA1) P2_1 ;
|
||||
__sbit __at (0xA0) P2_0 ;
|
||||
|
||||
/* IE 0xA8 */
|
||||
__sbit __at (0xAF) EA ; /* GLOBAL INTERRUPT ENABLE */
|
||||
__sbit __at (0xAD) ET2 ; /* TIMER 2 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAC) ES ; /* SERIAL PORT INTERRUPT ENABLE */
|
||||
__sbit __at (0xAB) ET1 ; /* TIMER 1 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAA) EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
|
||||
__sbit __at (0xA9) ET0 ; /* TIMER 0 INTERRUPT ENABLE */
|
||||
__sbit __at (0xA8) EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
|
||||
|
||||
/* P3 0xB0 */
|
||||
__sbit __at (0xB7) P3_7 ;
|
||||
__sbit __at (0xB6) P3_6 ;
|
||||
__sbit __at (0xB5) P3_5 ;
|
||||
__sbit __at (0xB4) P3_4 ;
|
||||
__sbit __at (0xB3) P3_3 ;
|
||||
__sbit __at (0xB2) P3_2 ;
|
||||
__sbit __at (0xB1) P3_1 ;
|
||||
__sbit __at (0xB0) P3_0 ;
|
||||
|
||||
/* IP 0xB8 */
|
||||
__sbit __at (0xBD) PT2 ; /* TIMER 2 PRIORITY */
|
||||
__sbit __at (0xBC) PS ; /* SERIAL PORT PRIORITY */
|
||||
__sbit __at (0xBB) PT1 ; /* TIMER 1 PRIORITY */
|
||||
__sbit __at (0xBA) PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
|
||||
__sbit __at (0xB9) PT0 ; /* TIMER 0 PRIORITY */
|
||||
__sbit __at (0xB8) PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
|
||||
|
||||
/* SMB0CN 0xC0 */
|
||||
__sbit __at (0xC7) BUSY ; /* SMBUS 0 BUSY */
|
||||
__sbit __at (0xC6) ENSMB ; /* SMBUS 0 ENABLE */
|
||||
__sbit __at (0xC5) STA ; /* SMBUS 0 START FLAG */
|
||||
__sbit __at (0xC4) STO ; /* SMBUS 0 STOP FLAG */
|
||||
__sbit __at (0xC3) SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
|
||||
__sbit __at (0xC2) AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
|
||||
__sbit __at (0xC1) SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
|
||||
__sbit __at (0xC0) SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
|
||||
|
||||
/* T2CON 0xC8 */
|
||||
__sbit __at (0xCF) TF2 ; /* TIMER 2 OVERFLOW FLAG */
|
||||
__sbit __at (0xCE) EXF2 ; /* EXTERNAL FLAG */
|
||||
__sbit __at (0xCD) RCLK ; /* RECEIVE CLOCK FLAG */
|
||||
__sbit __at (0xCC) TCLK ; /* TRANSMIT CLOCK FLAG */
|
||||
__sbit __at (0xCB) EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
|
||||
__sbit __at (0xCA) TR2 ; /* TIMER 2 ON/OFF CONTROL */
|
||||
__sbit __at (0xC9) CT2 ; /* TIMER OR COUNTER SELECT */
|
||||
__sbit __at (0xC8) CPRL2 ; /* CAPTURE OR RELOAD SELECT */
|
||||
|
||||
/* PSW 0xD0 */
|
||||
__sbit __at (0xD7) CY ; /* CARRY FLAG */
|
||||
__sbit __at (0xD6) AC ; /* AUXILIARY CARRY FLAG */
|
||||
__sbit __at (0xD5) F0 ; /* USER FLAG 0 */
|
||||
__sbit __at (0xD4) RS1 ; /* REGISTER BANK SELECT 1 */
|
||||
__sbit __at (0xD3) RS0 ; /* REGISTER BANK SELECT 0 */
|
||||
__sbit __at (0xD2) OV ; /* OVERFLOW FLAG */
|
||||
__sbit __at (0xD1) F1 ; /* USER FLAG 1 */
|
||||
__sbit __at (0xD0) P ; /* ACCUMULATOR PARITY FLAG */
|
||||
|
||||
/* PCA0CN 0xD8H */
|
||||
__sbit __at (0xDF) CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
|
||||
__sbit __at (0xDE) CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
|
||||
__sbit __at (0xDC) CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
|
||||
__sbit __at (0xDB) CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
|
||||
__sbit __at (0xDA) CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
|
||||
__sbit __at (0xD9) CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
|
||||
__sbit __at (0xD8) CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
|
||||
|
||||
/* ADC0CN 0xE8H */
|
||||
__sbit __at (0xEF) AD0EN ; /* ADC 0 ENABLE */
|
||||
__sbit __at (0xEE) AD0TM ; /* ADC 0 TRACK MODE */
|
||||
__sbit __at (0xED) AD0INT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
|
||||
__sbit __at (0xEC) AD0BUSY ; /* ADC 0 BUSY FLAG */
|
||||
__sbit __at (0xEB) ADSTM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */
|
||||
__sbit __at (0xEA) ADSTM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */
|
||||
__sbit __at (0xE9) AD0WINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */
|
||||
__sbit __at (0xE8) ADLJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
|
||||
|
||||
/* SPI0CN 0xF8H */
|
||||
__sbit __at (0xFF) SPIF ; /* SPI 0 INTERRUPT FLAG */
|
||||
__sbit __at (0xFE) WCOL ; /* SPI 0 WRITE COLLISION FLAG */
|
||||
__sbit __at (0xFD) MODF ; /* SPI 0 MODE FAULT FLAG */
|
||||
__sbit __at (0xFC) RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
|
||||
__sbit __at (0xFB) TXBSY ; /* SPI 0 TX BUSY FLAG */
|
||||
__sbit __at (0xFA) SLVSEL ; /* SPI 0 SLAVE SELECT */
|
||||
__sbit __at (0xF9) MSTEN ; /* SPI 0 MASTER ENABLE */
|
||||
__sbit __at (0xF8) SPIEN ; /* SPI 0 SPI ENABLE */
|
||||
|
||||
|
||||
/* Predefined SFR Bit Masks */
|
||||
|
||||
#define PCON_IDLE 0x01 /* PCON */
|
||||
#define PCON_STOP 0x02 /* PCON */
|
||||
#define TF3 0x80 /* TMR3CN */
|
||||
#define CPFIF 0x10 /* CPTnCN */
|
||||
#define CPRIF 0x20 /* CPTnCN */
|
||||
#define CPOUT 0x40 /* CPTnCN */
|
||||
#define ECCF 0x01 /* PCA0CPMn */
|
||||
#define PWM 0x02 /* PCA0CPMn */
|
||||
#define TOG 0x04 /* PCA0CPMn */
|
||||
#define MAT 0x08 /* PCA0CPMn */
|
||||
#define CAPN 0x10 /* PCA0CPMn */
|
||||
#define CAPP 0x20 /* PCA0CPMn */
|
||||
#define ECOM 0x40 /* PCA0CPMn */
|
||||
|
||||
#endif
|
||||
305
lib/mcs51/C8051F018.h
Normal file
305
lib/mcs51/C8051F018.h
Normal file
@@ -0,0 +1,305 @@
|
||||
/*---------------------------------------------------------------------------
|
||||
C8051F018.h - Register Declarations for the Cygnal/SiLabs C8051F018-F019
|
||||
Processor Range
|
||||
|
||||
Copyright (C) 2004, Maarten Brock, sourceforge.brock@dse.nl
|
||||
|
||||
This library is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the
|
||||
Free Software Foundation; either version 2, or (at your option) any
|
||||
later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this library; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
|
||||
MA 02110-1301, USA.
|
||||
|
||||
As a special exception, if you link this library with other files,
|
||||
some of which are compiled with SDCC, to produce an executable,
|
||||
this library does not by itself cause the resulting executable to
|
||||
be covered by the GNU General Public License. This exception does
|
||||
not however invalidate any other reasons why the executable file
|
||||
might be covered by the GNU General Public License.
|
||||
-------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef C8051F018_H
|
||||
#define C8051F018_H
|
||||
|
||||
|
||||
/* BYTE Registers */
|
||||
__sfr __at (0x80) P0 ; /* PORT 0 */
|
||||
__sfr __at (0x81) SP ; /* STACK POINTER */
|
||||
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
|
||||
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
|
||||
__sfr __at (0x87) PCON ; /* POWER CONTROL */
|
||||
__sfr __at (0x88) TCON ; /* TIMER CONTROL */
|
||||
__sfr __at (0x89) TMOD ; /* TIMER MODE */
|
||||
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
|
||||
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
|
||||
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
|
||||
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
|
||||
__sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
|
||||
__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
|
||||
__sfr __at (0x90) P1 ; /* PORT 1 */
|
||||
__sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */
|
||||
__sfr __at (0x92) TMR3RLL ; /* TIMER 3 RELOAD REGISTER - LOW BYTE */
|
||||
__sfr __at (0x93) TMR3RLH ; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */
|
||||
__sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */
|
||||
__sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */
|
||||
__sfr __at (0x98) SCON ; /* SERIAL PORT CONTROL */
|
||||
__sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
|
||||
__sfr __at (0x9A) SPI0CFG ; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */
|
||||
__sfr __at (0x9B) SPI0DAT ; /* SERIAL PERIPHERAL INTERFACE 0 DATA */
|
||||
__sfr __at (0x9D) SPI0CKR ; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */
|
||||
__sfr __at (0x9E) CPT0CN ; /* COMPARATOR 0 CONTROL */
|
||||
__sfr __at (0x9F) CPT1CN ; /* COMPARATOR 1 CONTROL */
|
||||
__sfr __at (0xA0) P2 ; /* PORT 2 */
|
||||
__sfr __at (0xA4) PRT0CF ; /* PORT 0 CONFIGURATION */
|
||||
__sfr __at (0xA5) PRT1CF ; /* PORT 1 CONFIGURATION */
|
||||
__sfr __at (0xA6) PRT2CF ; /* PORT 2 CONFIGURATION */
|
||||
__sfr __at (0xA7) PRT3CF ; /* PORT 3 CONFIGURATION */
|
||||
__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
|
||||
__sfr __at (0xAD) PRT1IF ; /* PORT 1 EXTERNAL INTERRUPT FLAGS */
|
||||
__sfr __at (0xAF) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
|
||||
__sfr __at (0xAF) _XPAGE ; /* XDATA/PDATA PAGE */
|
||||
__sfr __at (0xB0) P3 ; /* PORT 3 */
|
||||
__sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
|
||||
__sfr __at (0xB7) FLACL ; /* FLASH ACESS LIMIT */
|
||||
__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
|
||||
__sfr __at (0xBA) AMX0CF ; /* ADC 0 MUX CONFIGURATION */
|
||||
__sfr __at (0xBB) AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
|
||||
__sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */
|
||||
__sfr __at (0xBE) ADC0L ; /* ADC 0 DATA - LOW BYTE */
|
||||
__sfr __at (0xBF) ADC0H ; /* ADC 0 DATA - HIGH BYTE */
|
||||
__sfr __at (0xC0) SMB0CN ; /* SMBUS 0 CONTROL */
|
||||
__sfr __at (0xC1) SMB0STA ; /* SMBUS 0 STATUS */
|
||||
__sfr __at (0xC2) SMB0DAT ; /* SMBUS 0 DATA */
|
||||
__sfr __at (0xC3) SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
|
||||
__sfr __at (0xC4) ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
|
||||
__sfr __at (0xC5) ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xC6) ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
|
||||
__sfr __at (0xC7) ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
|
||||
__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
|
||||
__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
|
||||
__sfr __at (0xCF) SMB0CR ; /* SMBUS 0 CLOCK RATE */
|
||||
__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
|
||||
__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
|
||||
__sfr __at (0xD8) PCA0CN ; /* PCA 0 COUNTER CONTROL */
|
||||
__sfr __at (0xD9) PCA0MD ; /* PCA 0 COUNTER MODE */
|
||||
__sfr __at (0xDA) PCA0CPM0 ; /* CONTROL REGISTER FOR PCA 0 MODULE 0 */
|
||||
__sfr __at (0xDB) PCA0CPM1 ; /* CONTROL REGISTER FOR PCA 0 MODULE 1 */
|
||||
__sfr __at (0xDC) PCA0CPM2 ; /* CONTROL REGISTER FOR PCA 0 MODULE 2 */
|
||||
__sfr __at (0xDD) PCA0CPM3 ; /* CONTROL REGISTER FOR PCA 0 MODULE 3 */
|
||||
__sfr __at (0xDE) PCA0CPM4 ; /* CONTROL REGISTER FOR PCA 0 MODULE 4 */
|
||||
__sfr __at (0xE0) ACC ; /* ACCUMULATOR */
|
||||
__sfr __at (0xE1) XBR0 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 */
|
||||
__sfr __at (0xE2) XBR1 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 */
|
||||
__sfr __at (0xE3) XBR2 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 2 */
|
||||
__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
|
||||
__sfr __at (0xE7) EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
|
||||
__sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */
|
||||
__sfr __at (0xE9) PCA0L ; /* PCA 0 TIMER - LOW BYTE */
|
||||
__sfr __at (0xEA) PCA0CPL0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */
|
||||
__sfr __at (0xEB) PCA0CPL1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */
|
||||
__sfr __at (0xEC) PCA0CPL2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */
|
||||
__sfr __at (0xED) PCA0CPL3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */
|
||||
__sfr __at (0xEE) PCA0CPL4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */
|
||||
__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
|
||||
__sfr __at (0xF0) B ; /* B REGISTER */
|
||||
__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
|
||||
__sfr __at (0xF7) EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
|
||||
__sfr __at (0xF8) SPI0CN ; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL */
|
||||
__sfr __at (0xF9) PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
|
||||
__sfr __at (0xFA) PCA0CPH0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */
|
||||
__sfr __at (0xFB) PCA0CPH1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */
|
||||
__sfr __at (0xFC) PCA0CPH2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */
|
||||
__sfr __at (0xFD) PCA0CPH3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */
|
||||
__sfr __at (0xFE) PCA0CPH4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */
|
||||
__sfr __at (0xFF) WDTCN ; /* WATCHDOG TIMER CONTROL */
|
||||
|
||||
|
||||
/* WORD/DWORD Registers */
|
||||
|
||||
__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
|
||||
__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
|
||||
__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
|
||||
__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
|
||||
__sfr16 __at (0x9594) TMR3 ; /* TIMER 3 COUNTER */
|
||||
__sfr16 __at (0x9392) TMR3RL ; /* TIMER 3 CAPTURE REGISTER WORD */
|
||||
__sfr16 __at (0xBFBE) ADC0 ; /* ADC 0 DATA WORD */
|
||||
__sfr16 __at (0xC5C4) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */
|
||||
__sfr16 __at (0xC7C6) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */
|
||||
__sfr16 __at (0xF9E9) PCA0 ; /* PCA COUNTER */
|
||||
__sfr16 __at (0xFAEA) PCA0CP0 ; /* PCA CAPTURE 0 WORD */
|
||||
__sfr16 __at (0xFBEB) PCA0CP1 ; /* PCA CAPTURE 1 WORD */
|
||||
__sfr16 __at (0xFCEC) PCA0CP2 ; /* PCA CAPTURE 2 WORD */
|
||||
__sfr16 __at (0xFDED) PCA0CP3 ; /* PCA CAPTURE 3 WORD */
|
||||
__sfr16 __at (0xFEEE) PCA0CP4 ; /* PCA CAPTURE 4 WORD */
|
||||
|
||||
|
||||
/* BIT Registers */
|
||||
|
||||
/* P0 0x80 */
|
||||
__sbit __at (0x87) P0_7 ;
|
||||
__sbit __at (0x86) P0_6 ;
|
||||
__sbit __at (0x85) P0_5 ;
|
||||
__sbit __at (0x84) P0_4 ;
|
||||
__sbit __at (0x83) P0_3 ;
|
||||
__sbit __at (0x82) P0_2 ;
|
||||
__sbit __at (0x81) P0_1 ;
|
||||
__sbit __at (0x80) P0_0 ;
|
||||
|
||||
/* TCON 0x88 */
|
||||
__sbit __at (0x8F) TF1 ; /* TIMER 1 OVERFLOW FLAG */
|
||||
__sbit __at (0x8E) TR1 ; /* TIMER 1 ON/OFF CONTROL */
|
||||
__sbit __at (0x8D) TF0 ; /* TIMER 0 OVERFLOW FLAG */
|
||||
__sbit __at (0x8C) TR0 ; /* TIMER 0 ON/OFF CONTROL */
|
||||
__sbit __at (0x8B) IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
|
||||
__sbit __at (0x8A) IT1 ; /* EXT. INTERRUPT 1 TYPE */
|
||||
__sbit __at (0x89) IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
|
||||
__sbit __at (0x88) IT0 ; /* EXT. INTERRUPT 0 TYPE */
|
||||
|
||||
/* P1 0x90 */
|
||||
__sbit __at (0x97) P1_7 ;
|
||||
__sbit __at (0x96) P1_6 ;
|
||||
__sbit __at (0x95) P1_5 ;
|
||||
__sbit __at (0x94) P1_4 ;
|
||||
__sbit __at (0x93) P1_3 ;
|
||||
__sbit __at (0x92) P1_2 ;
|
||||
__sbit __at (0x91) P1_1 ;
|
||||
__sbit __at (0x90) P1_0 ;
|
||||
|
||||
/* SCON 0x98 */
|
||||
__sbit __at (0x9F) SM0 ; /* SERIAL MODE CONTROL BIT 0 */
|
||||
__sbit __at (0x9E) SM1 ; /* SERIAL MODE CONTROL BIT 1 */
|
||||
__sbit __at (0x9D) SM2 ; /* MULTIPROCESSOR COMMUNICATION ENABLE */
|
||||
__sbit __at (0x9C) REN ; /* RECEIVE ENABLE */
|
||||
__sbit __at (0x9B) TB8 ; /* TRANSMIT BIT 8 */
|
||||
__sbit __at (0x9A) RB8 ; /* RECEIVE BIT 8 */
|
||||
__sbit __at (0x99) TI ; /* TRANSMIT INTERRUPT FLAG */
|
||||
__sbit __at (0x98) RI ; /* RECEIVE INTERRUPT FLAG */
|
||||
|
||||
/* P2 0xA0 */
|
||||
__sbit __at (0xA7) P2_7 ;
|
||||
__sbit __at (0xA6) P2_6 ;
|
||||
__sbit __at (0xA5) P2_5 ;
|
||||
__sbit __at (0xA4) P2_4 ;
|
||||
__sbit __at (0xA3) P2_3 ;
|
||||
__sbit __at (0xA2) P2_2 ;
|
||||
__sbit __at (0xA1) P2_1 ;
|
||||
__sbit __at (0xA0) P2_0 ;
|
||||
|
||||
/* IE 0xA8 */
|
||||
__sbit __at (0xAF) EA ; /* GLOBAL INTERRUPT ENABLE */
|
||||
__sbit __at (0xAD) ET2 ; /* TIMER 2 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAC) ES ; /* SERIAL PORT INTERRUPT ENABLE */
|
||||
__sbit __at (0xAB) ET1 ; /* TIMER 1 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAA) EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
|
||||
__sbit __at (0xA9) ET0 ; /* TIMER 0 INTERRUPT ENABLE */
|
||||
__sbit __at (0xA8) EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
|
||||
|
||||
/* P3 0xB0 */
|
||||
__sbit __at (0xB7) P3_7 ;
|
||||
__sbit __at (0xB6) P3_6 ;
|
||||
__sbit __at (0xB5) P3_5 ;
|
||||
__sbit __at (0xB4) P3_4 ;
|
||||
__sbit __at (0xB3) P3_3 ;
|
||||
__sbit __at (0xB2) P3_2 ;
|
||||
__sbit __at (0xB1) P3_1 ;
|
||||
__sbit __at (0xB0) P3_0 ;
|
||||
|
||||
/* IP 0xB8 */
|
||||
__sbit __at (0xBD) PT2 ; /* TIMER 2 PRIORITY */
|
||||
__sbit __at (0xBC) PS ; /* SERIAL PORT PRIORITY */
|
||||
__sbit __at (0xBB) PT1 ; /* TIMER 1 PRIORITY */
|
||||
__sbit __at (0xBA) PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
|
||||
__sbit __at (0xB9) PT0 ; /* TIMER 0 PRIORITY */
|
||||
__sbit __at (0xB8) PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
|
||||
|
||||
/* SMB0CN 0xC0 */
|
||||
__sbit __at (0xC7) BUSY ; /* SMBUS 0 BUSY */
|
||||
__sbit __at (0xC6) ENSMB ; /* SMBUS 0 ENABLE */
|
||||
__sbit __at (0xC5) STA ; /* SMBUS 0 START FLAG */
|
||||
__sbit __at (0xC4) STO ; /* SMBUS 0 STOP FLAG */
|
||||
__sbit __at (0xC3) SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
|
||||
__sbit __at (0xC2) AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
|
||||
__sbit __at (0xC1) SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
|
||||
__sbit __at (0xC0) SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
|
||||
|
||||
/* T2CON 0xC8 */
|
||||
__sbit __at (0xCF) TF2 ; /* TIMER 2 OVERFLOW FLAG */
|
||||
__sbit __at (0xCE) EXF2 ; /* EXTERNAL FLAG */
|
||||
__sbit __at (0xCD) RCLK ; /* RECEIVE CLOCK FLAG */
|
||||
__sbit __at (0xCC) TCLK ; /* TRANSMIT CLOCK FLAG */
|
||||
__sbit __at (0xCB) EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
|
||||
__sbit __at (0xCA) TR2 ; /* TIMER 2 ON/OFF CONTROL */
|
||||
__sbit __at (0xC9) CT2 ; /* TIMER OR COUNTER SELECT */
|
||||
__sbit __at (0xC8) CPRL2 ; /* CAPTURE OR RELOAD SELECT */
|
||||
|
||||
/* PSW 0xD0 */
|
||||
__sbit __at (0xD7) CY ; /* CARRY FLAG */
|
||||
__sbit __at (0xD6) AC ; /* AUXILIARY CARRY FLAG */
|
||||
__sbit __at (0xD5) F0 ; /* USER FLAG 0 */
|
||||
__sbit __at (0xD4) RS1 ; /* REGISTER BANK SELECT 1 */
|
||||
__sbit __at (0xD3) RS0 ; /* REGISTER BANK SELECT 0 */
|
||||
__sbit __at (0xD2) OV ; /* OVERFLOW FLAG */
|
||||
__sbit __at (0xD1) F1 ; /* USER FLAG 1 */
|
||||
__sbit __at (0xD0) P ; /* ACCUMULATOR PARITY FLAG */
|
||||
|
||||
/* PCA0CN 0xD8H */
|
||||
__sbit __at (0xDF) CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
|
||||
__sbit __at (0xDE) CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
|
||||
__sbit __at (0xDC) CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
|
||||
__sbit __at (0xDB) CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
|
||||
__sbit __at (0xDA) CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
|
||||
__sbit __at (0xD9) CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
|
||||
__sbit __at (0xD8) CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
|
||||
|
||||
/* ADC0CN 0xE8H */
|
||||
__sbit __at (0xEF) AD0EN ; /* ADC 0 ENABLE */
|
||||
__sbit __at (0xEE) AD0TM ; /* ADC 0 TRACK MODE */
|
||||
__sbit __at (0xED) AD0INT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
|
||||
__sbit __at (0xEC) AD0BUSY ; /* ADC 0 BUSY FLAG */
|
||||
__sbit __at (0xEB) ADSTM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */
|
||||
__sbit __at (0xEA) ADSTM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */
|
||||
__sbit __at (0xE9) AD0WINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */
|
||||
__sbit __at (0xE8) ADLJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
|
||||
|
||||
/* SPI0CN 0xF8H */
|
||||
__sbit __at (0xFF) SPIF ; /* SPI 0 INTERRUPT FLAG */
|
||||
__sbit __at (0xFE) WCOL ; /* SPI 0 WRITE COLLISION FLAG */
|
||||
__sbit __at (0xFD) MODF ; /* SPI 0 MODE FAULT FLAG */
|
||||
__sbit __at (0xFC) RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
|
||||
__sbit __at (0xFB) TXBSY ; /* SPI 0 TX BUSY FLAG */
|
||||
__sbit __at (0xFA) SLVSEL ; /* SPI 0 SLAVE SELECT */
|
||||
__sbit __at (0xF9) MSTEN ; /* SPI 0 MASTER ENABLE */
|
||||
__sbit __at (0xF8) SPIEN ; /* SPI 0 SPI ENABLE */
|
||||
|
||||
|
||||
/* Predefined SFR Bit Masks */
|
||||
|
||||
#define PCON_IDLE 0x01 /* PCON */
|
||||
#define PCON_STOP 0x02 /* PCON */
|
||||
#define TF3 0x80 /* TMR3CN */
|
||||
#define CPFIF 0x10 /* CPTnCN */
|
||||
#define CPRIF 0x20 /* CPTnCN */
|
||||
#define CPOUT 0x40 /* CPTnCN */
|
||||
#define ECCF 0x01 /* PCA0CPMn */
|
||||
#define PWM 0x02 /* PCA0CPMn */
|
||||
#define TOG 0x04 /* PCA0CPMn */
|
||||
#define MAT 0x08 /* PCA0CPMn */
|
||||
#define CAPN 0x10 /* PCA0CPMn */
|
||||
#define CAPP 0x20 /* PCA0CPMn */
|
||||
#define ECOM 0x40 /* PCA0CPMn */
|
||||
|
||||
#endif
|
||||
378
lib/mcs51/C8051F020.h
Normal file
378
lib/mcs51/C8051F020.h
Normal file
@@ -0,0 +1,378 @@
|
||||
/*-------------------------------------------------------------------------
|
||||
C8051F020.h - Register Declarations for the Cygnal/SiLabs C8051F02x
|
||||
Processor Range
|
||||
|
||||
Copyright (C) 2004, Maarten Brock, sourceforge.brock@dse.nl
|
||||
|
||||
This library is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the
|
||||
Free Software Foundation; either version 2, or (at your option) any
|
||||
later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this library; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
|
||||
MA 02110-1301, USA.
|
||||
|
||||
As a special exception, if you link this library with other files,
|
||||
some of which are compiled with SDCC, to produce an executable,
|
||||
this library does not by itself cause the resulting executable to
|
||||
be covered by the GNU General Public License. This exception does
|
||||
not however invalidate any other reasons why the executable file
|
||||
might be covered by the GNU General Public License.
|
||||
-------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef C8051F020_H
|
||||
#define C8051F020_H
|
||||
|
||||
|
||||
/* BYTE Registers */
|
||||
__sfr __at (0x80) P0 ; /* PORT 0 */
|
||||
__sfr __at (0x81) SP ; /* STACK POINTER */
|
||||
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
|
||||
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
|
||||
__sfr __at (0x84) P4 ; /* PORT 4 */
|
||||
__sfr __at (0x85) P5 ; /* PORT 5 */
|
||||
__sfr __at (0x86) P6 ; /* PORT 6 */
|
||||
__sfr __at (0x87) PCON ; /* POWER CONTROL */
|
||||
__sfr __at (0x88) TCON ; /* TIMER CONTROL */
|
||||
__sfr __at (0x89) TMOD ; /* TIMER MODE */
|
||||
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
|
||||
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
|
||||
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
|
||||
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
|
||||
__sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
|
||||
__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
|
||||
__sfr __at (0x90) P1 ; /* PORT 1 */
|
||||
__sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */
|
||||
__sfr __at (0x92) TMR3RLL ; /* TIMER 3 RELOAD REGISTER - LOW BYTE */
|
||||
__sfr __at (0x93) TMR3RLH ; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */
|
||||
__sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */
|
||||
__sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */
|
||||
__sfr __at (0x96) P7 ; /* PORT 7 */
|
||||
__sfr __at (0x98) SCON ; /* UART0 CONTROL */
|
||||
__sfr __at (0x98) SCON0 ; /* UART0 CONTROL */
|
||||
__sfr __at (0x99) SBUF ; /* UART0 BUFFER */
|
||||
__sfr __at (0x99) SBUF0 ; /* UART0 BUFFER */
|
||||
__sfr __at (0x9A) SPI0CFG ; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */
|
||||
__sfr __at (0x9B) SPI0DAT ; /* SERIAL PERIPHERAL INTERFACE 0 DATA */
|
||||
__sfr __at (0x9C) ADC1 ; /* ADC 1 DATA */
|
||||
__sfr __at (0x9D) SPI0CKR ; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */
|
||||
__sfr __at (0x9E) CPT0CN ; /* COMPARATOR 0 CONTROL */
|
||||
__sfr __at (0x9F) CPT1CN ; /* COMPARATOR 1 CONTROL */
|
||||
__sfr __at (0xA0) P2 ; /* PORT 2 */
|
||||
__sfr __at (0xA1) EMI0TC ; /* External Memory Timing Control */
|
||||
__sfr __at (0xA3) EMI0CF ; /* EMIF CONFIGURATION */
|
||||
__sfr __at (0xA4) PRT0CF ; /* PORT 0 CONFIGURATION */
|
||||
__sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA5) PRT1CF ; /* PORT 1 CONFIGURATION */
|
||||
__sfr __at (0xA5) P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA6) PRT2CF ; /* PORT 2 CONFIGURATION */
|
||||
__sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA7) PRT3CF ; /* PORT 3 CONFIGURATION */
|
||||
__sfr __at (0xA7) P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
|
||||
__sfr __at (0xA9) SADDR0 ; /* UART0 Slave Address */
|
||||
__sfr __at (0xAA) ADC1CN ; /* ADC 1 CONTROL */
|
||||
__sfr __at (0xAB) ADC1CF ; /* ADC 1 CONFIGURATION */
|
||||
__sfr __at (0xAC) AMX1SL ; /* ADC 1 MUX CHANNEL SELECTION */
|
||||
__sfr __at (0xAD) P3IF ; /* PORT 3 EXTERNAL INTERRUPT FLAGS */
|
||||
__sfr __at (0xAE) SADEN1 ; /* UART1 Slave Address Enable */
|
||||
__sfr __at (0xAF) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
|
||||
__sfr __at (0xAF) _XPAGE ; /* XDATA/PDATA PAGE */
|
||||
__sfr __at (0xB0) P3 ; /* PORT 3 */
|
||||
__sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at (0xB5) P74OUT ; /* PORT 4 THROUGH 7 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
|
||||
__sfr __at (0xB7) FLACL ; /* FLASH ACESS LIMIT */
|
||||
__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
|
||||
__sfr __at (0xB9) SADEN0 ; /* UART0 Slave Address Enable */
|
||||
__sfr __at (0xBA) AMX0CF ; /* ADC 0 MUX CONFIGURATION */
|
||||
__sfr __at (0xBB) AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
|
||||
__sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */
|
||||
__sfr __at (0xBD) P1MDIN ; /* PORT 1 Input Mode */
|
||||
__sfr __at (0xBE) ADC0L ; /* ADC 0 DATA - LOW BYTE */
|
||||
__sfr __at (0xBF) ADC0H ; /* ADC 0 DATA - HIGH BYTE */
|
||||
__sfr __at (0xC0) SMB0CN ; /* SMBUS 0 CONTROL */
|
||||
__sfr __at (0xC1) SMB0STA ; /* SMBUS 0 STATUS */
|
||||
__sfr __at (0xC2) SMB0DAT ; /* SMBUS 0 DATA */
|
||||
__sfr __at (0xC3) SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
|
||||
__sfr __at (0xC4) ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
|
||||
__sfr __at (0xC5) ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xC6) ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
|
||||
__sfr __at (0xC7) ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
|
||||
__sfr __at (0xC9) T4CON ; /* TIMER 4 CONTROL */
|
||||
__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
|
||||
__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
|
||||
__sfr __at (0xCF) SMB0CR ; /* SMBUS 0 CLOCK RATE */
|
||||
__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
|
||||
__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
|
||||
__sfr __at (0xD2) DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
|
||||
__sfr __at (0xD3) DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xD4) DAC0CN ; /* DAC 0 CONTROL */
|
||||
__sfr __at (0xD5) DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
|
||||
__sfr __at (0xD6) DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xD7) DAC1CN ; /* DAC 1 CONTROL */
|
||||
__sfr __at (0xD8) PCA0CN ; /* PCA 0 COUNTER CONTROL */
|
||||
__sfr __at (0xD9) PCA0MD ; /* PCA 0 COUNTER MODE */
|
||||
__sfr __at (0xDA) PCA0CPM0 ; /* CONTROL REGISTER FOR PCA 0 MODULE 0 */
|
||||
__sfr __at (0xDB) PCA0CPM1 ; /* CONTROL REGISTER FOR PCA 0 MODULE 1 */
|
||||
__sfr __at (0xDC) PCA0CPM2 ; /* CONTROL REGISTER FOR PCA 0 MODULE 2 */
|
||||
__sfr __at (0xDD) PCA0CPM3 ; /* CONTROL REGISTER FOR PCA 0 MODULE 3 */
|
||||
__sfr __at (0xDE) PCA0CPM4 ; /* CONTROL REGISTER FOR PCA 0 MODULE 4 */
|
||||
__sfr __at (0xE0) ACC ; /* ACCUMULATOR */
|
||||
__sfr __at (0xE1) XBR0 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 */
|
||||
__sfr __at (0xE2) XBR1 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 */
|
||||
__sfr __at (0xE3) XBR2 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 2 */
|
||||
__sfr __at (0xE4) RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at (0xE5) RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
|
||||
__sfr __at (0xE7) EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
|
||||
__sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */
|
||||
__sfr __at (0xE9) PCA0L ; /* PCA 0 TIMER - LOW BYTE */
|
||||
__sfr __at (0xEA) PCA0CPL0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */
|
||||
__sfr __at (0xEB) PCA0CPL1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */
|
||||
__sfr __at (0xEC) PCA0CPL2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */
|
||||
__sfr __at (0xED) PCA0CPL3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */
|
||||
__sfr __at (0xEE) PCA0CPL4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */
|
||||
__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
|
||||
__sfr __at (0xF0) B ; /* B REGISTER */
|
||||
__sfr __at (0xF1) SCON1 ; /* UART1 CONTROL */
|
||||
__sfr __at (0xF2) SBUF1 ; /* UART1 DATA */
|
||||
__sfr __at (0xF3) SADDR1 ; /* UART1 Slave Address */
|
||||
__sfr __at (0xF4) TL4 ; /* TIMER 4 DATA - LOW BYTE */
|
||||
__sfr __at (0xF5) TH4 ; /* TIMER 4 DATA - HIGH BYTE */
|
||||
__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
|
||||
__sfr __at (0xF7) EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
|
||||
__sfr __at (0xF8) SPI0CN ; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL */
|
||||
__sfr __at (0xF9) PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
|
||||
__sfr __at (0xFA) PCA0CPH0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */
|
||||
__sfr __at (0xFB) PCA0CPH1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */
|
||||
__sfr __at (0xFC) PCA0CPH2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */
|
||||
__sfr __at (0xFD) PCA0CPH3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */
|
||||
__sfr __at (0xFE) PCA0CPH4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */
|
||||
__sfr __at (0xFF) WDTCN ; /* WATCHDOG TIMER CONTROL */
|
||||
|
||||
|
||||
/* WORD/DWORD Registers */
|
||||
|
||||
__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
|
||||
__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
|
||||
__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
|
||||
__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
|
||||
__sfr16 __at (0x9594) TMR3 ; /* TIMER 3 COUNTER */
|
||||
__sfr16 __at (0x9392) TMR3RL ; /* TIMER 3 CAPTURE REGISTER WORD */
|
||||
__sfr16 __at (0xF5F4) TMR4 ; /* TIMER 4 COUNTER */
|
||||
__sfr16 __at (0xE5E4) RCAP4 ; /* TIMER 4 CAPTURE REGISTER WORD */
|
||||
__sfr16 __at (0xBFBE) ADC0 ; /* ADC 0 DATA WORD */
|
||||
__sfr16 __at (0xC5C4) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */
|
||||
__sfr16 __at (0xC7C6) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */
|
||||
__sfr16 __at (0xD3D2) DAC0 ; /* DAC 0 REGISTER WORD */
|
||||
__sfr16 __at (0xD6D5) DAC1 ; /* DAC 1 REGISTER WORD */
|
||||
__sfr16 __at (0xF9E9) PCA0 ; /* PCA COUNTER */
|
||||
__sfr16 __at (0xFAEA) PCA0CP0 ; /* PCA CAPTURE 0 WORD */
|
||||
__sfr16 __at (0xFBEB) PCA0CP1 ; /* PCA CAPTURE 1 WORD */
|
||||
__sfr16 __at (0xFCEC) PCA0CP2 ; /* PCA CAPTURE 2 WORD */
|
||||
__sfr16 __at (0xFDED) PCA0CP3 ; /* PCA CAPTURE 3 WORD */
|
||||
__sfr16 __at (0xFEEE) PCA0CP4 ; /* PCA CAPTURE 4 WORD */
|
||||
|
||||
|
||||
/* BIT Registers */
|
||||
|
||||
/* P0 0x80 */
|
||||
__sbit __at (0x80) P0_0 ;
|
||||
__sbit __at (0x81) P0_1 ;
|
||||
__sbit __at (0x82) P0_2 ;
|
||||
__sbit __at (0x83) P0_3 ;
|
||||
__sbit __at (0x84) P0_4 ;
|
||||
__sbit __at (0x85) P0_5 ;
|
||||
__sbit __at (0x86) P0_6 ;
|
||||
__sbit __at (0x87) P0_7 ;
|
||||
|
||||
/* TCON 0x88 */
|
||||
__sbit __at (0x88) IT0 ; /* EXT. INTERRUPT 0 TYPE */
|
||||
__sbit __at (0x89) IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
|
||||
__sbit __at (0x8A) IT1 ; /* EXT. INTERRUPT 1 TYPE */
|
||||
__sbit __at (0x8B) IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
|
||||
__sbit __at (0x8C) TR0 ; /* TIMER 0 ON/OFF CONTROL */
|
||||
__sbit __at (0x8D) TF0 ; /* TIMER 0 OVERFLOW FLAG */
|
||||
__sbit __at (0x8E) TR1 ; /* TIMER 1 ON/OFF CONTROL */
|
||||
__sbit __at (0x8F) TF1 ; /* TIMER 1 OVERFLOW FLAG */
|
||||
|
||||
/* P1 0x90 */
|
||||
__sbit __at (0x90) P1_0 ;
|
||||
__sbit __at (0x91) P1_1 ;
|
||||
__sbit __at (0x92) P1_2 ;
|
||||
__sbit __at (0x93) P1_3 ;
|
||||
__sbit __at (0x94) P1_4 ;
|
||||
__sbit __at (0x95) P1_5 ;
|
||||
__sbit __at (0x96) P1_6 ;
|
||||
__sbit __at (0x97) P1_7 ;
|
||||
|
||||
/* SCON 0x98 */
|
||||
__sbit __at (0x98) RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
|
||||
__sbit __at (0x98) RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
|
||||
__sbit __at (0x99) TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
|
||||
__sbit __at (0x99) TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
|
||||
__sbit __at (0x9A) RB8 ; /* SCON.2 - RECEIVE BIT 8 */
|
||||
__sbit __at (0x9A) RB80 ; /* SCON.2 - RECEIVE BIT 8 */
|
||||
__sbit __at (0x9B) TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
|
||||
__sbit __at (0x9B) TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
|
||||
__sbit __at (0x9C) REN ; /* SCON.4 - RECEIVE ENABLE */
|
||||
__sbit __at (0x9C) REN0 ; /* SCON.4 - RECEIVE ENABLE */
|
||||
__sbit __at (0x9D) SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
|
||||
__sbit __at (0x9D) SM20 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
|
||||
__sbit __at (0x9D) MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
|
||||
__sbit __at (0x9E) SM1 ; /* SCON.6 - SERIAL MODE CONTROL BIT 1 */
|
||||
__sbit __at (0x9E) SM10 ; /* SCON.6 - SERIAL MODE CONTROL BIT 1 */
|
||||
__sbit __at (0x9F) SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
|
||||
__sbit __at (0x9F) SM00 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
|
||||
__sbit __at (0x9F) S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
|
||||
|
||||
/* P2 0xA0 */
|
||||
__sbit __at (0xA0) P2_0 ;
|
||||
__sbit __at (0xA1) P2_1 ;
|
||||
__sbit __at (0xA2) P2_2 ;
|
||||
__sbit __at (0xA3) P2_3 ;
|
||||
__sbit __at (0xA4) P2_4 ;
|
||||
__sbit __at (0xA5) P2_5 ;
|
||||
__sbit __at (0xA6) P2_6 ;
|
||||
__sbit __at (0xA7) P2_7 ;
|
||||
|
||||
/* IE 0xA8 */
|
||||
__sbit __at (0xA8) EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
|
||||
__sbit __at (0xA9) ET0 ; /* TIMER 0 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAA) EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
|
||||
__sbit __at (0xAB) ET1 ; /* TIMER 1 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAC) ES0 ; /* SERIAL PORT 0 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAC) ES ; /* SERIAL PORT 0 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAD) ET2 ; /* TIMER 2 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAF) EA ; /* GLOBAL INTERRUPT ENABLE */
|
||||
|
||||
/* P3 0xB0 */
|
||||
__sbit __at (0xB0) P3_0 ;
|
||||
__sbit __at (0xB1) P3_1 ;
|
||||
__sbit __at (0xB2) P3_2 ;
|
||||
__sbit __at (0xB3) P3_3 ;
|
||||
__sbit __at (0xB4) P3_4 ;
|
||||
__sbit __at (0xB5) P3_5 ;
|
||||
__sbit __at (0xB6) P3_6 ;
|
||||
__sbit __at (0xB7) P3_7 ;
|
||||
|
||||
/* IP 0xB8 */
|
||||
__sbit __at (0xB8) PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
|
||||
__sbit __at (0xB9) PT0 ; /* TIMER 0 PRIORITY */
|
||||
__sbit __at (0xBA) PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
|
||||
__sbit __at (0xBB) PT1 ; /* TIMER 1 PRIORITY */
|
||||
__sbit __at (0xBC) PS0 ; /* SERIAL PORT PRIORITY */
|
||||
__sbit __at (0xBC) PS ; /* SERIAL PORT PRIORITY */
|
||||
__sbit __at (0xBD) PT2 ; /* TIMER 2 PRIORITY */
|
||||
|
||||
/* SMB0CN 0xC0 */
|
||||
__sbit __at (0xC0) SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
|
||||
__sbit __at (0xC1) SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
|
||||
__sbit __at (0xC2) AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
|
||||
__sbit __at (0xC3) SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
|
||||
__sbit __at (0xC4) STO ; /* SMBUS 0 STOP FLAG */
|
||||
__sbit __at (0xC5) STA ; /* SMBUS 0 START FLAG */
|
||||
__sbit __at (0xC6) ENSMB ; /* SMBUS 0 ENABLE */
|
||||
__sbit __at (0xC7) BUSY ; /* SMBUS 0 BUSY */
|
||||
|
||||
/* T2CON 0xC8 */
|
||||
__sbit __at (0xC8) CPRL2 ; /* CAPTURE OR RELOAD SELECT */
|
||||
__sbit __at (0xC9) CT2 ; /* TIMER OR COUNTER SELECT */
|
||||
__sbit __at (0xCA) TR2 ; /* TIMER 2 ON/OFF CONTROL */
|
||||
__sbit __at (0xCB) EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
|
||||
__sbit __at (0xCC) TCLK ; /* TRANSMIT CLOCK FLAG */
|
||||
__sbit __at (0xCD) RCLK ; /* RECEIVE CLOCK FLAG */
|
||||
__sbit __at (0xCE) EXF2 ; /* EXTERNAL FLAG */
|
||||
__sbit __at (0xCF) TF2 ; /* TIMER 2 OVERFLOW FLAG */
|
||||
|
||||
/* PSW 0xD0 */
|
||||
__sbit __at (0xD0) P ; /* ACCUMULATOR PARITY FLAG */
|
||||
__sbit __at (0xD1) F1 ; /* USER FLAG 1 */
|
||||
__sbit __at (0xD2) OV ; /* OVERFLOW FLAG */
|
||||
__sbit __at (0xD3) RS0 ; /* REGISTER BANK SELECT 0 */
|
||||
__sbit __at (0xD4) RS1 ; /* REGISTER BANK SELECT 1 */
|
||||
__sbit __at (0xD5) F0 ; /* USER FLAG 0 */
|
||||
__sbit __at (0xD6) AC ; /* AUXILIARY CARRY FLAG */
|
||||
__sbit __at (0xD7) CY ; /* CARRY FLAG */
|
||||
|
||||
/* PCA0CN 0xD8H */
|
||||
__sbit __at (0xD8) CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
|
||||
__sbit __at (0xD9) CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
|
||||
__sbit __at (0xDA) CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
|
||||
__sbit __at (0xDB) CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
|
||||
__sbit __at (0xDC) CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
|
||||
__sbit __at (0xDE) CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
|
||||
__sbit __at (0xDF) CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
|
||||
|
||||
/* ADC0CN 0xE8H */
|
||||
__sbit __at (0xE8) ADLJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
|
||||
__sbit __at (0xE8) AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
|
||||
__sbit __at (0xE9) ADWINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */
|
||||
__sbit __at (0xE9) AD0WINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */
|
||||
__sbit __at (0xEA) ADSTM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */
|
||||
__sbit __at (0xEA) AD0CM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */
|
||||
__sbit __at (0xEB) ADSTM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */
|
||||
__sbit __at (0xEB) AD0CM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */
|
||||
__sbit __at (0xEC) ADBUSY ; /* ADC 0 BUSY FLAG */
|
||||
__sbit __at (0xEC) AD0BUSY ; /* ADC 0 BUSY FLAG */
|
||||
__sbit __at (0xED) ADCINT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
|
||||
__sbit __at (0xED) AD0INT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
|
||||
__sbit __at (0xEE) ADCTM ; /* ADC 0 TRACK MODE */
|
||||
__sbit __at (0xEE) AD0TM ; /* ADC 0 TRACK MODE */
|
||||
__sbit __at (0xEF) ADCEN ; /* ADC 0 ENABLE */
|
||||
__sbit __at (0xEF) AD0EN ; /* ADC 0 ENABLE */
|
||||
|
||||
/* SPI0CN 0xF8H */
|
||||
__sbit __at (0xF8) SPIEN ; /* SPI 0 SPI ENABLE */
|
||||
__sbit __at (0xF9) MSTEN ; /* SPI 0 MASTER ENABLE */
|
||||
__sbit __at (0xFA) SLVSEL ; /* SPI 0 SLAVE SELECT */
|
||||
__sbit __at (0xFB) TXBSY ; /* SPI 0 TX BUSY FLAG */
|
||||
__sbit __at (0xFC) RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
|
||||
__sbit __at (0xFD) MODF ; /* SPI 0 MODE FAULT FLAG */
|
||||
__sbit __at (0xFE) WCOL ; /* SPI 0 WRITE COLLISION FLAG */
|
||||
__sbit __at (0xFF) SPIF ; /* SPI 0 INTERRUPT FLAG */
|
||||
|
||||
|
||||
/* Predefined SFR Bit Masks */
|
||||
|
||||
#define PCON_IDLE 0x01 /* PCON */
|
||||
#define PCON_STOP 0x02 /* PCON */
|
||||
#define PCON_SMOD0 0x80 /* PCON */
|
||||
#define TF3 0x80 /* TMR3CN */
|
||||
#define CPFIF 0x10 /* CPTnCN */
|
||||
#define CPRIF 0x20 /* CPTnCN */
|
||||
#define CPOUT 0x40 /* CPTnCN */
|
||||
#define TR4 0x04 /* T4CON */
|
||||
#define TF4 0x80 /* T4CON */
|
||||
#define ECCF 0x01 /* PCA0CPMn */
|
||||
#define PWM 0x02 /* PCA0CPMn */
|
||||
#define TOG 0x04 /* PCA0CPMn */
|
||||
#define MAT 0x08 /* PCA0CPMn */
|
||||
#define CAPN 0x10 /* PCA0CPMn */
|
||||
#define CAPP 0x20 /* PCA0CPMn */
|
||||
#define ECOM 0x40 /* PCA0CPMn */
|
||||
#define PWM16 0x80 /* PCA0CPMn */
|
||||
#define PORSF 0x02 /* RSTSRC */
|
||||
#define SWRSF 0x10 /* RSTSRC */
|
||||
#define RI1 0x01 /* SCON1 */
|
||||
#define TI1 0x02 /* SCON1 */
|
||||
#define RB81 0x04 /* SCON1 */
|
||||
#define TB81 0x08 /* SCON1 */
|
||||
#define REN1 0x10 /* SCON1 */
|
||||
#define SM21 0x20 /* SCON1 */
|
||||
#define SM11 0x40 /* SCON1 */
|
||||
#define SM01 0x80 /* SCON1 */
|
||||
|
||||
#endif
|
||||
514
lib/mcs51/C8051F040.h
Normal file
514
lib/mcs51/C8051F040.h
Normal file
@@ -0,0 +1,514 @@
|
||||
/*-------------------------------------------------------------------------
|
||||
C8051F040.h - Register Declarations for the Cygnal/SiLabs C8051F04x
|
||||
Processor Range
|
||||
|
||||
Copyright (C) 2004, Maarten Brock, sourceforge.brock@dse.nl
|
||||
|
||||
This library is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the
|
||||
Free Software Foundation; either version 2, or (at your option) any
|
||||
later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this library; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
|
||||
MA 02110-1301, USA.
|
||||
|
||||
As a special exception, if you link this library with other files,
|
||||
some of which are compiled with SDCC, to produce an executable,
|
||||
this library does not by itself cause the resulting executable to
|
||||
be covered by the GNU General Public License. This exception does
|
||||
not however invalidate any other reasons why the executable file
|
||||
might be covered by the GNU General Public License.
|
||||
-------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef C8051F040_H
|
||||
#define C8051F040_H
|
||||
|
||||
|
||||
/* BYTE Registers */
|
||||
|
||||
/* All Pages */
|
||||
__sfr __at 0x80 P0 ; /* PORT 0 */
|
||||
__sfr __at 0x81 SP ; /* STACK POINTER */
|
||||
__sfr __at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
|
||||
__sfr __at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
|
||||
__sfr __at 0x84 SFRPAGE ; /* SFR PAGE SELECT */
|
||||
__sfr __at 0x85 SFRNEXT ; /* SFR STACK NEXT PAGE */
|
||||
__sfr __at 0x86 SFRLAST ; /* SFR STACK LAST PAGE */
|
||||
__sfr __at 0x87 PCON ; /* POWER CONTROL */
|
||||
__sfr __at 0x90 P1 ; /* PORT 1 */
|
||||
__sfr __at 0xA0 P2 ; /* PORT 2 */
|
||||
__sfr __at 0xA8 IE ; /* INTERRUPT ENABLE */
|
||||
__sfr __at 0xB0 P3 ; /* PORT 3 */
|
||||
__sfr __at 0xB8 IP ; /* INTERRUPT PRIORITY */
|
||||
__sfr __at 0xD0 PSW ; /* PROGRAM STATUS WORD */
|
||||
__sfr __at 0xE0 ACC ; /* ACCUMULATOR */
|
||||
__sfr __at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
|
||||
__sfr __at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
|
||||
__sfr __at 0xF0 B ; /* B REGISTER */
|
||||
__sfr __at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
|
||||
__sfr __at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
|
||||
__sfr __at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */
|
||||
|
||||
/* Page 0x00 */
|
||||
__sfr __at 0x88 TCON ; /* TIMER CONTROL */
|
||||
__sfr __at 0x89 TMOD ; /* TIMER MODE */
|
||||
__sfr __at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
|
||||
__sfr __at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
|
||||
__sfr __at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
|
||||
__sfr __at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
|
||||
__sfr __at 0x8E CKCON ; /* TIMER 0/1 CLOCK CONTROL */
|
||||
__sfr __at 0x8F PSCTL ; /* FLASH WRITE/ERASE CONTROL */
|
||||
__sfr __at 0x91 SSTA0 ; /* UART 0 STATUS */
|
||||
__sfr __at 0x98 SCON0 ; /* UART 0 CONTROL */
|
||||
__sfr __at 0x98 SCON ; /* UART 0 CONTROL */
|
||||
__sfr __at 0x99 SBUF0 ; /* UART 0 BUFFER */
|
||||
__sfr __at 0x99 SBUF ; /* UART 0 BUFFER */
|
||||
__sfr __at 0x9A SPI0CFG ; /* SPI 0 CONFIGURATION */
|
||||
__sfr __at 0x9B SPI0DAT ; /* SPI 0 DATA */
|
||||
__sfr __at 0x9D SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */
|
||||
__sfr __at 0xA1 EMI0TC ; /* EMIF TIMING CONTROL */
|
||||
__sfr __at 0xA2 EMI0CN ; /* EMIF CONTROL */
|
||||
__sfr __at 0xA2 _XPAGE ; /* XDATA/PDATA PAGE */
|
||||
__sfr __at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */
|
||||
__sfr __at 0xA9 SADDR0 ; /* UART 0 SLAVE ADDRESS */
|
||||
__sfr __at 0xB7 FLSCL ; /* FLASH SCALE */
|
||||
__sfr __at 0xB9 SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */
|
||||
__sfr __at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */
|
||||
__sfr __at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
|
||||
__sfr __at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
|
||||
__sfr __at 0xBD AMX0PRT ; /* ADC 0 PORT 3 I/O PIN SELECT */
|
||||
__sfr __at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */
|
||||
__sfr __at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */
|
||||
__sfr __at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */
|
||||
__sfr __at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */
|
||||
__sfr __at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */
|
||||
__sfr __at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
|
||||
__sfr __at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
|
||||
__sfr __at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
|
||||
__sfr __at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
|
||||
__sfr __at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
|
||||
__sfr __at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */
|
||||
__sfr __at 0xC9 TMR2CF ; /* TIMER 2 CONFIGURATION */
|
||||
__sfr __at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */
|
||||
__sfr __at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
|
||||
__sfr __at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */
|
||||
__sfr __at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
|
||||
__sfr __at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */
|
||||
__sfr __at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
|
||||
__sfr __at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
|
||||
__sfr __at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
|
||||
__sfr __at 0xD4 DAC0CN ; /* DAC 0 CONTROL */
|
||||
__sfr __at 0xD6 HVA0CN ; /* HIGH VOLTAGE DIFFERENTIAL AMP CONTROL */
|
||||
__sfr __at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */
|
||||
__sfr __at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */
|
||||
__sfr __at 0xDA PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */
|
||||
__sfr __at 0xDB PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */
|
||||
__sfr __at 0xDC PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */
|
||||
__sfr __at 0xDD PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */
|
||||
__sfr __at 0xDE PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */
|
||||
__sfr __at 0xDF PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */
|
||||
__sfr __at 0xE1 PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */
|
||||
__sfr __at 0xE2 PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */
|
||||
__sfr __at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
|
||||
__sfr __at 0xE9 PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */
|
||||
__sfr __at 0xEA PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */
|
||||
__sfr __at 0xEB PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */
|
||||
__sfr __at 0xEC PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */
|
||||
__sfr __at 0xED PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */
|
||||
__sfr __at 0xEE PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */
|
||||
__sfr __at 0xEF RSTSRC ; /* RESET SOURCE */
|
||||
__sfr __at 0xF8 SPI0CN ; /* SPI 0 CONTROL */
|
||||
__sfr __at 0xF9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */
|
||||
__sfr __at 0xFA PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
|
||||
__sfr __at 0xFB PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */
|
||||
__sfr __at 0xFC PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */
|
||||
__sfr __at 0xFD PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */
|
||||
__sfr __at 0xFE PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */
|
||||
|
||||
/* Page 0x01 */
|
||||
__sfr __at 0x88 CPT0CN ; /* COMPARATOR 0 CONTROL */
|
||||
__sfr __at 0x89 CPT0MD ; /* COMPARATOR 0 CONFIGURATION */
|
||||
__sfr __at 0x98 SCON1 ; /* UART 1 CONTROL */
|
||||
__sfr __at 0x99 SBUF1 ; /* UART 1 BUFFER */
|
||||
__sfr __at 0xC0 CAN0STA ; /* CAN 0 STATUS */
|
||||
__sfr __at 0xC8 TMR3CN ; /* TIMER 3 CONTROL */
|
||||
__sfr __at 0xC9 TMR3CF ; /* TIMER 3 CONFIGURATION */
|
||||
__sfr __at 0xCA RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at 0xCB RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at 0xCC TMR3L ; /* TIMER 3 - LOW BYTE */
|
||||
__sfr __at 0xCD TMR3H ; /* TIMER 3 - HIGH BYTE */
|
||||
__sfr __at 0xD2 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
|
||||
__sfr __at 0xD3 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
|
||||
__sfr __at 0xD4 DAC1CN ; /* DAC 1 CONTROL */
|
||||
__sfr __at 0xD8 CAN0DATL ; /* CAN 0 DATA REGISTER LOW */
|
||||
__sfr __at 0xD9 CAN0DATH ; /* CAN 0 DATA REGISTER HIGH */
|
||||
__sfr __at 0xDA CAN0ADR ; /* CAN 0 ADDRESS */
|
||||
__sfr __at 0xDB CAN0TST ; /* CAN 0 TEST REGISTER */
|
||||
__sfr __at 0xF8 CAN0CN ; /* CAN 0 CONTROL */
|
||||
|
||||
/* Page 0x02 */
|
||||
__sfr __at 0x88 CPT1CN ; /* COMPARATOR 1 CONTROL */
|
||||
__sfr __at 0x89 CPT1MD ; /* COMPARATOR 1 CONFIGURATION */
|
||||
__sfr __at 0xBA AMX2CF ; /* ADC 2 MUX CONFIGURATION */
|
||||
__sfr __at 0xBB AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */
|
||||
__sfr __at 0xBC ADC2CF ; /* ADC 2 CONFIGURATION */
|
||||
__sfr __at 0xBE ADC2 ; /* ADC 2 DATA */
|
||||
__sfr __at 0xC4 ADC2GT ; /* ADC 2 GREATER-THAN REGISTER */
|
||||
__sfr __at 0xC6 ADC2LT ; /* ADC 2 LESS-THAN REGISTER */
|
||||
__sfr __at 0xC8 TMR4CN ; /* TIMER 4 CONTROL */
|
||||
__sfr __at 0xC9 TMR4CF ; /* TIMER 4 CONFIGURATION */
|
||||
__sfr __at 0xCA RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at 0xCB RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at 0xCC TMR4L ; /* TIMER 4 - LOW BYTE */
|
||||
__sfr __at 0xCD TMR4H ; /* TIMER 4 - HIGH BYTE */
|
||||
__sfr __at 0xE8 ADC2CN ; /* ADC 2 CONTROL */
|
||||
|
||||
/* Page 0x03 */
|
||||
__sfr __at 0x88 CPT2CN ; /* COMPARATOR 2 CONTROL */
|
||||
__sfr __at 0x89 CPT2MD ; /* COMPARATOR 2 CONFIGURATION */
|
||||
|
||||
/* Page 0x0F */
|
||||
__sfr __at 0x8A OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at 0x8B OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
|
||||
__sfr __at 0x8C OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at 0x96 SFRPGCN ; /* SFR PAGE CONTROL */
|
||||
__sfr __at 0x97 CLKSEL ; /* SYSTEM CLOCK SELECT */
|
||||
__sfr __at 0x9C P4MDOUT ; /* PORT 4 OUTPUT MODE */
|
||||
__sfr __at 0x9D P5MDOUT ; /* PORT 5 OUTPUT MODE */
|
||||
__sfr __at 0x9E P6MDOUT ; /* PORT 6 OUTPUT MODE */
|
||||
__sfr __at 0x9F P7MDOUT ; /* PORT 7 OUTPUT MODE */
|
||||
__sfr __at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE */
|
||||
__sfr __at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE */
|
||||
__sfr __at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at 0xAD P1MDIN ; /* PORT 1 INPUT MODE */
|
||||
__sfr __at 0xAE P2MDIN ; /* PORT 2 INPUT MODE */
|
||||
__sfr __at 0xAF P3MDIN ; /* PORT 3 INPUT MODE */
|
||||
__sfr __at 0xB7 FLACL ; /* FLASH ACCESS LIMIT */
|
||||
__sfr __at 0xC8 P4 ; /* PORT 4 */
|
||||
__sfr __at 0xD8 P5 ; /* PORT 5 */
|
||||
__sfr __at 0xE1 XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */
|
||||
__sfr __at 0xE2 XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */
|
||||
__sfr __at 0xE3 XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */
|
||||
__sfr __at 0xE4 XBR3 ; /* CROSSBAR CONFIGURATION REGISTER 3 */
|
||||
__sfr __at 0xE8 P6 ; /* PORT 6 */
|
||||
__sfr __at 0xF8 P7 ; /* PORT 7 */
|
||||
|
||||
/*
|
||||
Do NOT use sfr16 for CAN0DAT !
|
||||
*/
|
||||
|
||||
/* BIT Registers */
|
||||
|
||||
/* P0 0x80 */
|
||||
__sbit __at 0x80 P0_0 ;
|
||||
__sbit __at 0x81 P0_1 ;
|
||||
__sbit __at 0x82 P0_2 ;
|
||||
__sbit __at 0x83 P0_3 ;
|
||||
__sbit __at 0x84 P0_4 ;
|
||||
__sbit __at 0x85 P0_5 ;
|
||||
__sbit __at 0x86 P0_6 ;
|
||||
__sbit __at 0x87 P0_7 ;
|
||||
|
||||
/* TCON 0x88 */
|
||||
__sbit __at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */
|
||||
__sbit __at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
|
||||
__sbit __at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */
|
||||
__sbit __at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
|
||||
__sbit __at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */
|
||||
__sbit __at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */
|
||||
__sbit __at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */
|
||||
__sbit __at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */
|
||||
|
||||
/* CPT0CN 0x88 */
|
||||
__sbit __at 0x88 CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */
|
||||
__sbit __at 0x89 CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */
|
||||
__sbit __at 0x8A CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */
|
||||
__sbit __at 0x8B CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */
|
||||
__sbit __at 0x8C CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */
|
||||
__sbit __at 0x8D CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */
|
||||
__sbit __at 0x8E CP0OUT ; /* COMPARATOR 0 OUTPUT */
|
||||
__sbit __at 0x8F CP0EN ; /* COMPARATOR 0 ENABLE */
|
||||
|
||||
/* CPT1CN 0x88 */
|
||||
__sbit __at 0x88 CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */
|
||||
__sbit __at 0x89 CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */
|
||||
__sbit __at 0x8A CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */
|
||||
__sbit __at 0x8B CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */
|
||||
__sbit __at 0x8C CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */
|
||||
__sbit __at 0x8D CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */
|
||||
__sbit __at 0x8E CP1OUT ; /* COMPARATOR 1 OUTPUT */
|
||||
__sbit __at 0x8F CP1EN ; /* COMPARATOR 1 ENABLE */
|
||||
|
||||
/* CPT2CN 0x88 */
|
||||
__sbit __at 0x88 CP2HYN0 ; /* COMPARATOR 2 NEGATIVE HYSTERESIS 0 */
|
||||
__sbit __at 0x89 CP2HYN1 ; /* COMPARATOR 2 NEGATIVE HYSTERESIS 1 */
|
||||
__sbit __at 0x8A CP2HYP0 ; /* COMPARATOR 2 POSITIVE HYSTERESIS 0 */
|
||||
__sbit __at 0x8B CP2HYP1 ; /* COMPARATOR 2 POSITIVE HYSTERESIS 1 */
|
||||
__sbit __at 0x8C CP2FIF ; /* COMPARATOR 2 FALLING EDGE INTERRUPT */
|
||||
__sbit __at 0x8D CP2RIF ; /* COMPARATOR 2 RISING EDGE INTERRUPT */
|
||||
__sbit __at 0x8E CP2OUT ; /* COMPARATOR 2 OUTPUT */
|
||||
__sbit __at 0x8F CP2EN ; /* COMPARATOR 2 ENABLE */
|
||||
|
||||
/* P1 0x90 */
|
||||
__sbit __at 0x90 P1_0 ;
|
||||
__sbit __at 0x91 P1_1 ;
|
||||
__sbit __at 0x92 P1_2 ;
|
||||
__sbit __at 0x93 P1_3 ;
|
||||
__sbit __at 0x94 P1_4 ;
|
||||
__sbit __at 0x95 P1_5 ;
|
||||
__sbit __at 0x96 P1_6 ;
|
||||
__sbit __at 0x97 P1_7 ;
|
||||
|
||||
/* SCON0 0x98 */
|
||||
__sbit __at 0x98 RI0 ; /* UART 0 RX INTERRUPT FLAG */
|
||||
__sbit __at 0x98 RI ; /* UART 0 RX INTERRUPT FLAG */
|
||||
__sbit __at 0x99 TI0 ; /* UART 0 TX INTERRUPT FLAG */
|
||||
__sbit __at 0x99 TI ; /* UART 0 TX INTERRUPT FLAG */
|
||||
__sbit __at 0x9A RB80 ; /* UART 0 RX BIT 8 */
|
||||
__sbit __at 0x9B TB80 ; /* UART 0 TX BIT 8 */
|
||||
__sbit __at 0x9C REN0 ; /* UART 0 RX ENABLE */
|
||||
__sbit __at 0x9C REN ; /* UART 0 RX ENABLE */
|
||||
__sbit __at 0x9D SM20 ; /* UART 0 MULTIPROCESSOR EN */
|
||||
__sbit __at 0x9E SM10 ; /* UART 0 MODE 1 */
|
||||
__sbit __at 0x9F SM00 ; /* UART 0 MODE 0 */
|
||||
|
||||
/* SCON1 0x98 */
|
||||
__sbit __at 0x98 RI1 ; /* UART 1 RX INTERRUPT FLAG */
|
||||
__sbit __at 0x99 TI1 ; /* UART 1 TX INTERRUPT FLAG */
|
||||
__sbit __at 0x9A RB81 ; /* UART 1 RX BIT 8 */
|
||||
__sbit __at 0x9B TB81 ; /* UART 1 TX BIT 8 */
|
||||
__sbit __at 0x9C REN1 ; /* UART 1 RX ENABLE */
|
||||
__sbit __at 0x9D MCE1 ; /* UART 1 MCE */
|
||||
__sbit __at 0x9F S1MODE ; /* UART 1 MODE */
|
||||
|
||||
/* P2 0xA0 */
|
||||
__sbit __at 0xA0 P2_0 ;
|
||||
__sbit __at 0xA1 P2_1 ;
|
||||
__sbit __at 0xA2 P2_2 ;
|
||||
__sbit __at 0xA3 P2_3 ;
|
||||
__sbit __at 0xA4 P2_4 ;
|
||||
__sbit __at 0xA5 P2_5 ;
|
||||
__sbit __at 0xA6 P2_6 ;
|
||||
__sbit __at 0xA7 P2_7 ;
|
||||
|
||||
/* IE 0xA8 */
|
||||
__sbit __at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
|
||||
__sbit __at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */
|
||||
__sbit __at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
|
||||
__sbit __at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */
|
||||
__sbit __at 0xAC ES0 ; /* UART0 INTERRUPT ENABLE */
|
||||
__sbit __at 0xAC ES ; /* UART0 INTERRUPT ENABLE */
|
||||
__sbit __at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */
|
||||
__sbit __at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */
|
||||
|
||||
/* P3 0xB0 */
|
||||
__sbit __at 0xB0 P3_0 ;
|
||||
__sbit __at 0xB1 P3_1 ;
|
||||
__sbit __at 0xB2 P3_2 ;
|
||||
__sbit __at 0xB3 P3_3 ;
|
||||
__sbit __at 0xB4 P3_4 ;
|
||||
__sbit __at 0xB5 P3_5 ;
|
||||
__sbit __at 0xB6 P3_6 ;
|
||||
__sbit __at 0xB7 P3_7 ;
|
||||
|
||||
/* IP 0xB8 */
|
||||
__sbit __at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
|
||||
__sbit __at 0xB9 PT0 ; /* TIMER 0 PRIORITY */
|
||||
__sbit __at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
|
||||
__sbit __at 0xBB PT1 ; /* TIMER 1 PRIORITY */
|
||||
__sbit __at 0xBC PS0 ; /* SERIAL PORT PRIORITY */
|
||||
__sbit __at 0xBC PS ; /* SERIAL PORT PRIORITY */
|
||||
__sbit __at 0xBD PT2 ; /* TIMER 2 PRIORITY */
|
||||
|
||||
/* SMB0CN 0xC0 */
|
||||
__sbit __at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
|
||||
__sbit __at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
|
||||
__sbit __at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
|
||||
__sbit __at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
|
||||
__sbit __at 0xC4 STO ; /* SMBUS 0 STOP FLAG */
|
||||
__sbit __at 0xC5 STA ; /* SMBUS 0 START FLAG */
|
||||
__sbit __at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */
|
||||
__sbit __at 0xC7 BUSY ; /* SMBUS 0 BUSY */
|
||||
|
||||
/* CAN0STA 0xC0 */
|
||||
__sbit __at 0xC3 CANTXOK ; /* CAN TRANSMITTED A MESSAGE SUCCESSFULLY */
|
||||
__sbit __at 0xC4 CANRXOK ; /* CAN RECEIVED A MESSAGE SUCCESSFULLY */
|
||||
__sbit __at 0xC5 CANEPASS; /* CAN ERROR PASSIVE */
|
||||
__sbit __at 0xC6 CANEWARN; /* CAN WARNING STATUS */
|
||||
__sbit __at 0xC7 CANBOFF ; /* CAN BUSOFF STATUS */
|
||||
|
||||
/* TMR2CN 0xC8 */
|
||||
__sbit __at 0xC8 CPRL2 ; /* TIMER 2 CAPTURE SELECT */
|
||||
__sbit __at 0xC9 CT2 ; /* TIMER 2 COUNTER SELECT */
|
||||
__sbit __at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */
|
||||
__sbit __at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
|
||||
__sbit __at 0xCE EXF2 ; /* TIMER 2 EXTERNAL FLAG */
|
||||
__sbit __at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */
|
||||
|
||||
/* TMR3CN 0xC8 */
|
||||
__sbit __at 0xC8 CPRL3 ; /* TIMER 3 CAPTURE SELECT */
|
||||
__sbit __at 0xC9 CT3 ; /* TIMER 3 COUNTER SELECT */
|
||||
__sbit __at 0xCA TR3 ; /* TIMER 3 ON/OFF CONTROL */
|
||||
__sbit __at 0xCB EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */
|
||||
__sbit __at 0xCE EXF3 ; /* TIMER 3 EXTERNAL FLAG */
|
||||
__sbit __at 0xCF TF3 ; /* TIMER 3 OVERFLOW FLAG */
|
||||
|
||||
/* TMR4CN 0xC8 */
|
||||
__sbit __at 0xC8 CPRL4 ; /* TIMER 4 CAPTURE SELECT */
|
||||
__sbit __at 0xC9 CT4 ; /* TIMER 4 COUNTER SELECT */
|
||||
__sbit __at 0xCA TR4 ; /* TIMER 4 ON/OFF CONTROL */
|
||||
__sbit __at 0xCB EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */
|
||||
__sbit __at 0xCE EXF4 ; /* TIMER 4 EXTERNAL FLAG */
|
||||
__sbit __at 0xCF TF4 ; /* TIMER 4 OVERFLOW FLAG */
|
||||
|
||||
/* P4 0xC8 */
|
||||
__sbit __at 0xC8 P4_0 ;
|
||||
__sbit __at 0xC9 P4_1 ;
|
||||
__sbit __at 0xCA P4_2 ;
|
||||
__sbit __at 0xCB P4_3 ;
|
||||
__sbit __at 0xCC P4_4 ;
|
||||
__sbit __at 0xCD P4_5 ;
|
||||
__sbit __at 0xCE P4_6 ;
|
||||
__sbit __at 0xCF P4_7 ;
|
||||
|
||||
/* PSW 0xD0 */
|
||||
__sbit __at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */
|
||||
__sbit __at 0xD1 F1 ; /* USER FLAG 1 */
|
||||
__sbit __at 0xD2 OV ; /* OVERFLOW FLAG */
|
||||
__sbit __at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */
|
||||
__sbit __at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */
|
||||
__sbit __at 0xD5 F0 ; /* USER FLAG 0 */
|
||||
__sbit __at 0xD6 AC ; /* AUXILIARY CARRY FLAG */
|
||||
__sbit __at 0xD7 CY ; /* CARRY FLAG */
|
||||
|
||||
/* PCA0CN 0xD8 */
|
||||
__sbit __at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
|
||||
__sbit __at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
|
||||
__sbit __at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
|
||||
__sbit __at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
|
||||
__sbit __at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
|
||||
__sbit __at 0xDD CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */
|
||||
__sbit __at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
|
||||
__sbit __at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
|
||||
|
||||
/* P5 0xD8 */
|
||||
__sbit __at 0xD8 P5_0 ;
|
||||
__sbit __at 0xD9 P5_1 ;
|
||||
__sbit __at 0xDA P5_2 ;
|
||||
__sbit __at 0xDB P5_3 ;
|
||||
__sbit __at 0xDC P5_4 ;
|
||||
__sbit __at 0xDD P5_5 ;
|
||||
__sbit __at 0xDE P5_6 ;
|
||||
__sbit __at 0xDF P5_7 ;
|
||||
|
||||
/* ADC0CN 0xE8 */
|
||||
__sbit __at 0xE8 AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
|
||||
__sbit __at 0xE9 AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */
|
||||
__sbit __at 0xEA AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */
|
||||
__sbit __at 0xEB AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */
|
||||
__sbit __at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */
|
||||
__sbit __at 0xED AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */
|
||||
__sbit __at 0xEE AD0TM ; /* ADC 0 TRACK MODE */
|
||||
__sbit __at 0xEF AD0EN ; /* ADC 0 ENABLE */
|
||||
|
||||
/* ADC2CN 0xE8 */
|
||||
__sbit __at 0xE8 AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */
|
||||
__sbit __at 0xE9 AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */
|
||||
__sbit __at 0xEA AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */
|
||||
__sbit __at 0xEB AD2CM2 ; /* ADC 2 CONVERT START MODE BIT 2 */
|
||||
__sbit __at 0xEC AD2BUSY ; /* ADC 2 BUSY FLAG */
|
||||
__sbit __at 0xED AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */
|
||||
__sbit __at 0xEE AD2TM ; /* ADC 2 TRACK MODE */
|
||||
__sbit __at 0xEF AD2EN ; /* ADC 2 ENABLE */
|
||||
|
||||
/* P6 0xE8 */
|
||||
__sbit __at 0xE8 P6_0 ;
|
||||
__sbit __at 0xE9 P6_1 ;
|
||||
__sbit __at 0xEA P6_2 ;
|
||||
__sbit __at 0xEB P6_3 ;
|
||||
__sbit __at 0xEC P6_4 ;
|
||||
__sbit __at 0xED P6_5 ;
|
||||
__sbit __at 0xEE P6_6 ;
|
||||
__sbit __at 0xEF P6_7 ;
|
||||
|
||||
/* SPI0CN 0xF8 */
|
||||
__sbit __at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */
|
||||
__sbit __at 0xF9 TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */
|
||||
__sbit __at 0xFA NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */
|
||||
__sbit __at 0xFB NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */
|
||||
__sbit __at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
|
||||
__sbit __at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */
|
||||
__sbit __at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */
|
||||
__sbit __at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */
|
||||
|
||||
/* CAN0CN 0xF8 */
|
||||
__sbit __at 0xF8 CANINIT ; /* CAN INITIALIZATION */
|
||||
__sbit __at 0xF9 CANIE ; /* CAN MODULE INTERRUPT ENABLE */
|
||||
__sbit __at 0xFA CANSIE ; /* CAN STATUS CHANGE INTERRUPT ENABLE */
|
||||
__sbit __at 0xFB CANEIE ; /* CAN ERROR INTERRUPT ENABLE */
|
||||
__sbit __at 0xFC CANIF ; /* CAN INTERRUPT FLAG */
|
||||
__sbit __at 0xFD CANDAR ; /* CAN DISABLE AUTOMATIC RETRANSMISSION */
|
||||
__sbit __at 0xFE CANCCE ; /* CAN CONFIGURATION CHANGE ENABLE */
|
||||
__sbit __at 0xFF CANTEST ; /* CAN TEST MODE ENABLE */
|
||||
|
||||
/* P7 0xF8 */
|
||||
__sbit __at 0xF8 P7_0 ;
|
||||
__sbit __at 0xF9 P7_1 ;
|
||||
__sbit __at 0xFA P7_2 ;
|
||||
__sbit __at 0xFB P7_3 ;
|
||||
__sbit __at 0xFC P7_4 ;
|
||||
__sbit __at 0xFD P7_5 ;
|
||||
__sbit __at 0xFE P7_6 ;
|
||||
__sbit __at 0xFF P7_7 ;
|
||||
|
||||
|
||||
/* Predefined SFR Bit Masks */
|
||||
|
||||
#define IDLE 0x01 /* PCON */
|
||||
#define STOP 0x02 /* PCON */
|
||||
#define ECCF 0x01 /* PCA0CPMn */
|
||||
#define PWM 0x02 /* PCA0CPMn */
|
||||
#define TOG 0x04 /* PCA0CPMn */
|
||||
#define MAT 0x08 /* PCA0CPMn */
|
||||
#define CAPN 0x10 /* PCA0CPMn */
|
||||
#define CAPP 0x20 /* PCA0CPMn */
|
||||
#define ECOM 0x40 /* PCA0CPMn */
|
||||
#define PWM16 0x80 /* PCA0CPMn */
|
||||
#define PORSF 0x02 /* RSTSRC */
|
||||
#define SWRSF 0x10 /* RSTSRC */
|
||||
|
||||
|
||||
/* SFR PAGE DEFINITIONS */
|
||||
|
||||
#define CONFIG_PAGE 0x0F /* SYSTEM AND PORT CONFIGURATION PAGE */
|
||||
#define LEGACY_PAGE 0x00 /* LEGACY SFR PAGE */
|
||||
#define TIMER01_PAGE 0x00 /* TIMER 0 AND TIMER 1 */
|
||||
#define CPT0_PAGE 0x01 /* COMPARATOR 0 */
|
||||
#define CPT1_PAGE 0x02 /* COMPARATOR 1 */
|
||||
#define CPT2_PAGE 0x03 /* COMPARATOR 2 */
|
||||
#define UART0_PAGE 0x00 /* UART 0 */
|
||||
#define UART1_PAGE 0x01 /* UART 1 */
|
||||
#define SPI0_PAGE 0x00 /* SPI 0 */
|
||||
#define EMI0_PAGE 0x00 /* EXTERNAL MEMORY INTERFACE */
|
||||
#define ADC0_PAGE 0x00 /* ADC 0 */
|
||||
#define ADC2_PAGE 0x02 /* ADC 2 */
|
||||
#define SMB0_PAGE 0x00 /* SMBUS 0 */
|
||||
#define TMR2_PAGE 0x00 /* TIMER 2 */
|
||||
#define TMR3_PAGE 0x01 /* TIMER 3 */
|
||||
#define TMR4_PAGE 0x02 /* TIMER 4 */
|
||||
#define DAC0_PAGE 0x00 /* DAC 0 */
|
||||
#define DAC1_PAGE 0x01 /* DAC 1 */
|
||||
#define PCA0_PAGE 0x00 /* PCA 0 */
|
||||
#define CAN0_PAGE 0x01 /* CAN 0 */
|
||||
|
||||
#endif
|
||||
560
lib/mcs51/C8051F060.h
Normal file
560
lib/mcs51/C8051F060.h
Normal file
@@ -0,0 +1,560 @@
|
||||
/*-------------------------------------------------------------------------
|
||||
C8051F060.h - Register Declarations for the Cygnal/SiLabs C8051F06x
|
||||
Processor Range
|
||||
|
||||
Copyright (C) 2004, Maarten Brock, sourceforge.brock@dse.nl
|
||||
|
||||
This library is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the
|
||||
Free Software Foundation; either version 2, or (at your option) any
|
||||
later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this library; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
|
||||
MA 02110-1301, USA.
|
||||
|
||||
As a special exception, if you link this library with other files,
|
||||
some of which are compiled with SDCC, to produce an executable,
|
||||
this library does not by itself cause the resulting executable to
|
||||
be covered by the GNU General Public License. This exception does
|
||||
not however invalidate any other reasons why the executable file
|
||||
might be covered by the GNU General Public License.
|
||||
-------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef C8051F060_H
|
||||
#define C8051F060_H
|
||||
|
||||
|
||||
/* BYTE Registers */
|
||||
|
||||
/* All Pages */
|
||||
__sfr __at 0x80 P0 ; /* PORT 0 */
|
||||
__sfr __at 0x81 SP ; /* STACK POINTER */
|
||||
__sfr __at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
|
||||
__sfr __at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
|
||||
__sfr __at 0x84 SFRPAGE ; /* SFR PAGE SELECT */
|
||||
__sfr __at 0x85 SFRNEXT ; /* SFR STACK NEXT PAGE */
|
||||
__sfr __at 0x86 SFRLAST ; /* SFR STACK LAST PAGE */
|
||||
__sfr __at 0x87 PCON ; /* POWER CONTROL */
|
||||
__sfr __at 0x90 P1 ; /* PORT 1 */
|
||||
__sfr __at 0xA0 P2 ; /* PORT 2 */
|
||||
__sfr __at 0xA8 IE ; /* INTERRUPT ENABLE */
|
||||
__sfr __at 0xB0 P3 ; /* PORT 3 */
|
||||
__sfr __at 0xB8 IP ; /* INTERRUPT PRIORITY */
|
||||
__sfr __at 0xD0 PSW ; /* PROGRAM STATUS WORD */
|
||||
__sfr __at 0xE0 ACC ; /* ACCUMULATOR */
|
||||
__sfr __at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
|
||||
__sfr __at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
|
||||
__sfr __at 0xF0 B ; /* B REGISTER */
|
||||
__sfr __at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
|
||||
__sfr __at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
|
||||
__sfr __at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */
|
||||
|
||||
/* Page 0x00 */
|
||||
__sfr __at 0x88 TCON ; /* TIMER CONTROL */
|
||||
__sfr __at 0x89 TMOD ; /* TIMER MODE */
|
||||
__sfr __at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
|
||||
__sfr __at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
|
||||
__sfr __at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
|
||||
__sfr __at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
|
||||
__sfr __at 0x8E CKCON ; /* TIMER 0/1 CLOCK CONTROL */
|
||||
__sfr __at 0x8F PSCTL ; /* FLASH WRITE/ERASE CONTROL */
|
||||
__sfr __at 0x91 SSTA0 ; /* UART 0 STATUS */
|
||||
__sfr __at 0x98 SCON0 ; /* UART 0 CONTROL */
|
||||
__sfr __at 0x98 SCON ; /* UART 0 CONTROL */
|
||||
__sfr __at 0x99 SBUF0 ; /* UART 0 BUFFER */
|
||||
__sfr __at 0x99 SBUF ; /* UART 0 BUFFER */
|
||||
__sfr __at 0x9A SPI0CFG ; /* SPI 0 CONFIGURATION */
|
||||
__sfr __at 0x9B SPI0DAT ; /* SPI 0 DATA */
|
||||
__sfr __at 0x9D SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */
|
||||
__sfr __at 0xA1 EMI0TC ; /* EMIF TIMING CONTROL */
|
||||
__sfr __at 0xA2 EMI0CN ; /* EMIF CONTROL */
|
||||
__sfr __at 0xA2 _XPAGE ; /* XDATA/PDATA PAGE */
|
||||
__sfr __at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */
|
||||
__sfr __at 0xA9 SADDR0 ; /* UART 0 SLAVE ADDRESS */
|
||||
__sfr __at 0xB7 FLSCL ; /* FLASH SCALE */
|
||||
__sfr __at 0xB9 SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */
|
||||
__sfr __at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
|
||||
__sfr __at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
|
||||
__sfr __at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */
|
||||
__sfr __at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */
|
||||
__sfr __at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */
|
||||
__sfr __at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */
|
||||
__sfr __at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */
|
||||
__sfr __at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
|
||||
__sfr __at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
|
||||
__sfr __at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
|
||||
__sfr __at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
|
||||
__sfr __at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
|
||||
__sfr __at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */
|
||||
__sfr __at 0xC9 TMR2CF ; /* TIMER 2 CONFIGURATION */
|
||||
__sfr __at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */
|
||||
__sfr __at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
|
||||
__sfr __at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */
|
||||
__sfr __at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
|
||||
__sfr __at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */
|
||||
__sfr __at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
|
||||
__sfr __at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
|
||||
__sfr __at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
|
||||
__sfr __at 0xD4 DAC0CN ; /* DAC 0 CONTROL */
|
||||
__sfr __at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */
|
||||
__sfr __at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */
|
||||
__sfr __at 0xDA PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */
|
||||
__sfr __at 0xDB PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */
|
||||
__sfr __at 0xDC PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */
|
||||
__sfr __at 0xDD PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */
|
||||
__sfr __at 0xDE PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */
|
||||
__sfr __at 0xDF PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */
|
||||
__sfr __at 0xE1 PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */
|
||||
__sfr __at 0xE2 PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */
|
||||
__sfr __at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
|
||||
__sfr __at 0xE9 PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */
|
||||
__sfr __at 0xEA PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */
|
||||
__sfr __at 0xEB PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */
|
||||
__sfr __at 0xEC PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */
|
||||
__sfr __at 0xED PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */
|
||||
__sfr __at 0xEE PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */
|
||||
__sfr __at 0xEF RSTSRC ; /* RESET SOURCE */
|
||||
__sfr __at 0xF8 SPI0CN ; /* SPI 0 CONTROL */
|
||||
__sfr __at 0xF9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */
|
||||
__sfr __at 0xFA PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
|
||||
__sfr __at 0xFB PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */
|
||||
__sfr __at 0xFC PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */
|
||||
__sfr __at 0xFD PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */
|
||||
__sfr __at 0xFE PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */
|
||||
|
||||
/* Page 0x01 */
|
||||
__sfr __at 0x88 CPT0CN ; /* COMPARATOR 0 CONTROL */
|
||||
__sfr __at 0x89 CPT0MD ; /* COMPARATOR 0 CONFIGURATION */
|
||||
__sfr __at 0x98 SCON1 ; /* UART 1 CONTROL */
|
||||
__sfr __at 0x99 SBUF1 ; /* UART 1 BUFFER */
|
||||
__sfr __at 0xBC ADC1CF ; /* ADC 1 CONFIGURATION */
|
||||
__sfr __at 0xBE ADC1L ; /* ADC 1 DATA - LOW BYTE */
|
||||
__sfr __at 0xBF ADC1H ; /* ADC 1 DATA - HIGH BYTE */
|
||||
__sfr __at 0xC0 CAN0STA ; /* CAN 0 STATUS */
|
||||
__sfr __at 0xC8 TMR3CN ; /* TIMER 3 CONTROL */
|
||||
__sfr __at 0xC9 TMR3CF ; /* TIMER 3 CONFIGURATION */
|
||||
__sfr __at 0xCA RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at 0xCB RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at 0xCC TMR3L ; /* TIMER 3 - LOW BYTE */
|
||||
__sfr __at 0xCD TMR3H ; /* TIMER 3 - HIGH BYTE */
|
||||
__sfr __at 0xD1 REF1CN ; /* VOLTAGE REFERENCE 1 CONTROL */
|
||||
__sfr __at 0xD2 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
|
||||
__sfr __at 0xD3 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
|
||||
__sfr __at 0xD4 DAC1CN ; /* DAC 1 CONTROL */
|
||||
__sfr __at 0xD8 CAN0DATL ; /* CAN 0 DATA REGISTER LOW */
|
||||
__sfr __at 0xD9 CAN0DATH ; /* CAN 0 DATA REGISTER HIGH */
|
||||
__sfr __at 0xDA CAN0ADR ; /* CAN 0 ADDRESS */
|
||||
__sfr __at 0xDB CAN0TST ; /* CAN 0 TEST REGISTER */
|
||||
__sfr __at 0xE8 ADC1CN ; /* ADC 1 CONTROL */
|
||||
__sfr __at 0xF8 CAN0CN ; /* CAN 0 CONTROL */
|
||||
|
||||
/* Page 0x02 */
|
||||
__sfr __at 0x88 CPT1CN ; /* COMPARATOR 1 CONTROL */
|
||||
__sfr __at 0x89 CPT1MD ; /* COMPARATOR 1 CONFIGURATION */
|
||||
__sfr __at 0xBA AMX2CF ; /* ADC 2 MUX CONFIGURATION */
|
||||
__sfr __at 0xBB AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */
|
||||
__sfr __at 0xBC ADC2CF ; /* ADC 2 CONFIGURATION */
|
||||
__sfr __at 0xBE ADC2L ; /* ADC 2 DATA - LOW BYTE */
|
||||
__sfr __at 0xBF ADC2H ; /* ADC 2 DATA - HIGH BYTE */
|
||||
__sfr __at 0xC4 ADC2GTL ; /* ADC 2 GREATER-THAN REGISTER - LOW BYTE */
|
||||
__sfr __at 0xC5 ADC2GTH ; /* ADC 2 GREATER-THAN REGISTER - HIGH BYTE */
|
||||
__sfr __at 0xC6 ADC2LTL ; /* ADC 2 LESS-THAN REGISTER - LOW BYTE */
|
||||
__sfr __at 0xC7 ADC2LTH ; /* ADC 2 LESS-THAN REGISTER - HIGH BYTE */
|
||||
__sfr __at 0xC8 TMR4CN ; /* TIMER 4 CONTROL */
|
||||
__sfr __at 0xC9 TMR4CF ; /* TIMER 4 CONFIGURATION */
|
||||
__sfr __at 0xCA RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at 0xCB RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at 0xCC TMR4L ; /* TIMER 4 - LOW BYTE */
|
||||
__sfr __at 0xCD TMR4H ; /* TIMER 4 - HIGH BYTE */
|
||||
__sfr __at 0xD1 REF2CN ; /* VOLTAGE REFERENCE 2 CONTROL */
|
||||
__sfr __at 0xE8 ADC2CN ; /* ADC 2 CONTROL */
|
||||
|
||||
/* Page 0x03 */
|
||||
__sfr __at 0x88 CPT2CN ; /* COMPARATOR 2 CONTROL */
|
||||
__sfr __at 0x89 CPT2MD ; /* COMPARATOR 2 CONFIGURATION */
|
||||
__sfr __at 0xD8 DMA0CN ; /* DMA0 CONTROL */
|
||||
__sfr __at 0xD9 DMA0DAL ; /* DMA0 DATA ADDRESS BEGINNING LOW BYTE */
|
||||
__sfr __at 0xDA DMA0DAH ; /* DMA0 DATA ADDRESS BEGINNING HIGH BYTE */
|
||||
__sfr __at 0xDB DMA0DSL ; /* DMA0 DATA ADDRESS POINTER LOW BYTE */
|
||||
__sfr __at 0xDC DMA0DSH ; /* DMA0 DATA ADDRESS POINTER HIGH BYTE */
|
||||
__sfr __at 0xDD DMA0IPT ; /* DMA0 INSTRUCTION WRITE ADDRESS */
|
||||
__sfr __at 0xDE DMA0IDT ; /* DMA0 INSTRUCTION WRITE DATA */
|
||||
__sfr __at 0xF8 DMA0CF ; /* DMA0 CONFIGURATION */
|
||||
__sfr __at 0xF9 DMA0CTL ; /* DMA0 REPEAT COUNTER LIMIT LOW BYTE */
|
||||
__sfr __at 0xFA DMA0CTH ; /* DMA0 REPEAT COUNTER LIMIT HIGH BYTE */
|
||||
__sfr __at 0xFB DMA0CSL ; /* DMA0 REPEAT COUNTER STATUS LOW BYTE */
|
||||
__sfr __at 0xFC DMA0CSH ; /* DMA0 REPEAT COUNTER STATUS HIGH BYTE */
|
||||
__sfr __at 0xFD DMA0BND ; /* DMA0 INSTRUCTION BOUNDARY */
|
||||
__sfr __at 0xFE DMA0ISW ; /* DMA0 INSTRUCTION STATUS */
|
||||
|
||||
/* Page 0x0F */
|
||||
__sfr __at 0x8A OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at 0x8B OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
|
||||
__sfr __at 0x8C OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at 0x96 SFRPGCN ; /* SFR PAGE CONTROL */
|
||||
__sfr __at 0x97 CLKSEL ; /* SYSTEM CLOCK SELECT */
|
||||
__sfr __at 0x9C P4MDOUT ; /* PORT 4 OUTPUT MODE */
|
||||
__sfr __at 0x9D P5MDOUT ; /* PORT 5 OUTPUT MODE */
|
||||
__sfr __at 0x9E P6MDOUT ; /* PORT 6 OUTPUT MODE */
|
||||
__sfr __at 0x9F P7MDOUT ; /* PORT 7 OUTPUT MODE */
|
||||
__sfr __at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE */
|
||||
__sfr __at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE */
|
||||
__sfr __at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at 0xAD P1MDIN ; /* PORT 1 INPUT MODE */
|
||||
__sfr __at 0xAE P2MDIN ; /* PORT 2 INPUT MODE */
|
||||
__sfr __at 0xB7 FLACL ; /* FLASH ACCESS LIMIT */
|
||||
__sfr __at 0xBA ADC0CPT ; /* ADC0 CALIBRATION POINTER */
|
||||
__sfr __at 0xBB ADC0CCF ; /* ADC0 CALIBRATION COEFFICIENT */
|
||||
__sfr __at 0xC8 P4 ; /* PORT 4 */
|
||||
__sfr __at 0xD8 P5 ; /* PORT 5 */
|
||||
__sfr __at 0xE1 XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */
|
||||
__sfr __at 0xE2 XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */
|
||||
__sfr __at 0xE3 XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */
|
||||
__sfr __at 0xE4 XBR3 ; /* CROSSBAR CONFIGURATION REGISTER 3 */
|
||||
__sfr __at 0xE8 P6 ; /* PORT 6 */
|
||||
__sfr __at 0xF8 P7 ; /* PORT 7 */
|
||||
|
||||
|
||||
/* BIT Registers */
|
||||
|
||||
/* P0 0x80 */
|
||||
__sbit __at 0x80 P0_0 ;
|
||||
__sbit __at 0x81 P0_1 ;
|
||||
__sbit __at 0x82 P0_2 ;
|
||||
__sbit __at 0x83 P0_3 ;
|
||||
__sbit __at 0x84 P0_4 ;
|
||||
__sbit __at 0x85 P0_5 ;
|
||||
__sbit __at 0x86 P0_6 ;
|
||||
__sbit __at 0x87 P0_7 ;
|
||||
|
||||
/* TCON 0x88 */
|
||||
__sbit __at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */
|
||||
__sbit __at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
|
||||
__sbit __at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */
|
||||
__sbit __at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
|
||||
__sbit __at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */
|
||||
__sbit __at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */
|
||||
__sbit __at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */
|
||||
__sbit __at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */
|
||||
|
||||
/* CPT0CN 0x88 */
|
||||
__sbit __at 0x88 CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */
|
||||
__sbit __at 0x89 CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */
|
||||
__sbit __at 0x8A CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */
|
||||
__sbit __at 0x8B CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */
|
||||
__sbit __at 0x8C CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */
|
||||
__sbit __at 0x8D CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */
|
||||
__sbit __at 0x8E CP0OUT ; /* COMPARATOR 0 OUTPUT */
|
||||
__sbit __at 0x8F CP0EN ; /* COMPARATOR 0 ENABLE */
|
||||
|
||||
/* CPT1CN 0x88 */
|
||||
__sbit __at 0x88 CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */
|
||||
__sbit __at 0x89 CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */
|
||||
__sbit __at 0x8A CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */
|
||||
__sbit __at 0x8B CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */
|
||||
__sbit __at 0x8C CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */
|
||||
__sbit __at 0x8D CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */
|
||||
__sbit __at 0x8E CP1OUT ; /* COMPARATOR 1 OUTPUT */
|
||||
__sbit __at 0x8F CP1EN ; /* COMPARATOR 1 ENABLE */
|
||||
|
||||
/* CPT2CN 0x88 */
|
||||
__sbit __at 0x88 CP2HYN0 ; /* COMPARATOR 2 NEGATIVE HYSTERESIS 0 */
|
||||
__sbit __at 0x89 CP2HYN1 ; /* COMPARATOR 2 NEGATIVE HYSTERESIS 1 */
|
||||
__sbit __at 0x8A CP2HYP0 ; /* COMPARATOR 2 POSITIVE HYSTERESIS 0 */
|
||||
__sbit __at 0x8B CP2HYP1 ; /* COMPARATOR 2 POSITIVE HYSTERESIS 1 */
|
||||
__sbit __at 0x8C CP2FIF ; /* COMPARATOR 2 FALLING EDGE INTERRUPT */
|
||||
__sbit __at 0x8D CP2RIF ; /* COMPARATOR 2 RISING EDGE INTERRUPT */
|
||||
__sbit __at 0x8E CP2OUT ; /* COMPARATOR 2 OUTPUT */
|
||||
__sbit __at 0x8F CP2EN ; /* COMPARATOR 2 ENABLE */
|
||||
|
||||
/* P1 0x90 */
|
||||
__sbit __at 0x90 P1_0 ;
|
||||
__sbit __at 0x91 P1_1 ;
|
||||
__sbit __at 0x92 P1_2 ;
|
||||
__sbit __at 0x93 P1_3 ;
|
||||
__sbit __at 0x94 P1_4 ;
|
||||
__sbit __at 0x95 P1_5 ;
|
||||
__sbit __at 0x96 P1_6 ;
|
||||
__sbit __at 0x97 P1_7 ;
|
||||
|
||||
/* SCON0 0x98 */
|
||||
__sbit __at 0x98 RI0 ; /* UART 0 RX INTERRUPT FLAG */
|
||||
__sbit __at 0x98 RI ; /* UART 0 RX INTERRUPT FLAG */
|
||||
__sbit __at 0x99 TI0 ; /* UART 0 TX INTERRUPT FLAG */
|
||||
__sbit __at 0x99 TI ; /* UART 0 TX INTERRUPT FLAG */
|
||||
__sbit __at 0x9A RB80 ; /* UART 0 RX BIT 8 */
|
||||
__sbit __at 0x9B TB80 ; /* UART 0 TX BIT 8 */
|
||||
__sbit __at 0x9C REN0 ; /* UART 0 RX ENABLE */
|
||||
__sbit __at 0x9C REN ; /* UART 0 RX ENABLE */
|
||||
__sbit __at 0x9D SM20 ; /* UART 0 MULTIPROCESSOR EN */
|
||||
__sbit __at 0x9E SM10 ; /* UART 0 MODE 1 */
|
||||
__sbit __at 0x9F SM00 ; /* UART 0 MODE 0 */
|
||||
|
||||
/* SCON1 0x98 */
|
||||
__sbit __at 0x98 RI1 ; /* UART 1 RX INTERRUPT FLAG */
|
||||
__sbit __at 0x99 TI1 ; /* UART 1 TX INTERRUPT FLAG */
|
||||
__sbit __at 0x9A RB81 ; /* UART 1 RX BIT 8 */
|
||||
__sbit __at 0x9B TB81 ; /* UART 1 TX BIT 8 */
|
||||
__sbit __at 0x9C REN1 ; /* UART 1 RX ENABLE */
|
||||
__sbit __at 0x9D MCE1 ; /* UART 1 MCE */
|
||||
__sbit __at 0x9F S1MODE ; /* UART 1 MODE */
|
||||
|
||||
/* P2 0xA0 */
|
||||
__sbit __at 0xA0 P2_0 ;
|
||||
__sbit __at 0xA1 P2_1 ;
|
||||
__sbit __at 0xA2 P2_2 ;
|
||||
__sbit __at 0xA3 P2_3 ;
|
||||
__sbit __at 0xA4 P2_4 ;
|
||||
__sbit __at 0xA5 P2_5 ;
|
||||
__sbit __at 0xA6 P2_6 ;
|
||||
__sbit __at 0xA7 P2_7 ;
|
||||
|
||||
/* IE 0xA8 */
|
||||
__sbit __at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
|
||||
__sbit __at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */
|
||||
__sbit __at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
|
||||
__sbit __at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */
|
||||
__sbit __at 0xAC ES0 ; /* UART0 INTERRUPT ENABLE */
|
||||
__sbit __at 0xAC ES ; /* UART0 INTERRUPT ENABLE */
|
||||
__sbit __at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */
|
||||
__sbit __at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */
|
||||
|
||||
/* P3 0xB0 */
|
||||
__sbit __at 0xB0 P3_0 ;
|
||||
__sbit __at 0xB1 P3_1 ;
|
||||
__sbit __at 0xB2 P3_2 ;
|
||||
__sbit __at 0xB3 P3_3 ;
|
||||
__sbit __at 0xB4 P3_4 ;
|
||||
__sbit __at 0xB5 P3_5 ;
|
||||
__sbit __at 0xB6 P3_6 ;
|
||||
__sbit __at 0xB7 P3_7 ;
|
||||
|
||||
/* IP 0xB8 */
|
||||
__sbit __at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
|
||||
__sbit __at 0xB9 PT0 ; /* TIMER 0 PRIORITY */
|
||||
__sbit __at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
|
||||
__sbit __at 0xBB PT1 ; /* TIMER 1 PRIORITY */
|
||||
__sbit __at 0xBC PS0 ; /* SERIAL PORT PRIORITY */
|
||||
__sbit __at 0xBC PS ; /* SERIAL PORT PRIORITY */
|
||||
__sbit __at 0xBD PT2 ; /* TIMER 2 PRIORITY */
|
||||
|
||||
/* SMB0CN 0xC0 */
|
||||
__sbit __at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
|
||||
__sbit __at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
|
||||
__sbit __at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
|
||||
__sbit __at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
|
||||
__sbit __at 0xC4 STO ; /* SMBUS 0 STOP FLAG */
|
||||
__sbit __at 0xC5 STA ; /* SMBUS 0 START FLAG */
|
||||
__sbit __at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */
|
||||
__sbit __at 0xC7 BUSY ; /* SMBUS 0 BUSY */
|
||||
|
||||
/* CAN0STA 0xC0 */
|
||||
__sbit __at 0xC3 CANTXOK ; /* CAN TRANSMITTED A MESSAGE SUCCESSFULLY */
|
||||
__sbit __at 0xC4 CANRXOK ; /* CAN RECEIVED A MESSAGE SUCCESSFULLY */
|
||||
__sbit __at 0xC5 CANEPASS; /* CAN ERROR PASSIVE */
|
||||
__sbit __at 0xC6 CANEWARN; /* CAN WARNING STATUS */
|
||||
__sbit __at 0xC7 CANBOFF ; /* CAN BUSOFF STATUS */
|
||||
|
||||
/* TMR2CN 0xC8 */
|
||||
__sbit __at 0xC8 CPRL2 ; /* TIMER 2 CAPTURE SELECT */
|
||||
__sbit __at 0xC9 CT2 ; /* TIMER 2 COUNTER SELECT */
|
||||
__sbit __at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */
|
||||
__sbit __at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
|
||||
__sbit __at 0xCE EXF2 ; /* TIMER 2 EXTERNAL FLAG */
|
||||
__sbit __at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */
|
||||
|
||||
/* TMR3CN 0xC8 */
|
||||
__sbit __at 0xC8 CPRL3 ; /* TIMER 3 CAPTURE SELECT */
|
||||
__sbit __at 0xC9 CT3 ; /* TIMER 3 COUNTER SELECT */
|
||||
__sbit __at 0xCA TR3 ; /* TIMER 3 ON/OFF CONTROL */
|
||||
__sbit __at 0xCB EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */
|
||||
__sbit __at 0xCE EXF3 ; /* TIMER 3 EXTERNAL FLAG */
|
||||
__sbit __at 0xCF TF3 ; /* TIMER 3 OVERFLOW FLAG */
|
||||
|
||||
/* TMR4CN 0xC8 */
|
||||
__sbit __at 0xC8 CPRL4 ; /* TIMER 4 CAPTURE SELECT */
|
||||
__sbit __at 0xC9 CT4 ; /* TIMER 4 COUNTER SELECT */
|
||||
__sbit __at 0xCA TR4 ; /* TIMER 4 ON/OFF CONTROL */
|
||||
__sbit __at 0xCB EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */
|
||||
__sbit __at 0xCE EXF4 ; /* TIMER 4 EXTERNAL FLAG */
|
||||
__sbit __at 0xCF TF4 ; /* TIMER 4 OVERFLOW FLAG */
|
||||
|
||||
/* P4 0xC8 */
|
||||
__sbit __at 0xC8 P4_0 ;
|
||||
__sbit __at 0xC9 P4_1 ;
|
||||
__sbit __at 0xCA P4_2 ;
|
||||
__sbit __at 0xCB P4_3 ;
|
||||
__sbit __at 0xCC P4_4 ;
|
||||
__sbit __at 0xCD P4_5 ;
|
||||
__sbit __at 0xCE P4_6 ;
|
||||
__sbit __at 0xCF P4_7 ;
|
||||
|
||||
/* PSW 0xD0 */
|
||||
__sbit __at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */
|
||||
__sbit __at 0xD1 F1 ; /* USER FLAG 1 */
|
||||
__sbit __at 0xD2 OV ; /* OVERFLOW FLAG */
|
||||
__sbit __at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */
|
||||
__sbit __at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */
|
||||
__sbit __at 0xD5 F0 ; /* USER FLAG 0 */
|
||||
__sbit __at 0xD6 AC ; /* AUXILIARY CARRY FLAG */
|
||||
__sbit __at 0xD7 CY ; /* CARRY FLAG */
|
||||
|
||||
/* PCA0CN 0xD8 */
|
||||
__sbit __at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
|
||||
__sbit __at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
|
||||
__sbit __at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
|
||||
__sbit __at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
|
||||
__sbit __at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
|
||||
__sbit __at 0xDD CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */
|
||||
__sbit __at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
|
||||
__sbit __at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
|
||||
|
||||
/* DMA0CN 0xD8 */
|
||||
__sbit __at 0xD8 DMA0DO0 ; /* ADC0 Data Overflow Warning Flag */
|
||||
__sbit __at 0xD9 DMA0DO1 ; /* ADC1 Data Overflow Warning Flag */
|
||||
__sbit __at 0xDA DMA0DOE ; /* Data Overflow Warning Interrupt Enable */
|
||||
__sbit __at 0xDB DMA0DE0 ; /* ADC0 Data Overflow Error Flag */
|
||||
__sbit __at 0xDC DMA0DE1 ; /* ADC1 Data Overflow Error Flag */
|
||||
__sbit __at 0xDD DMA0MD ; /* DMA0 Mode Select */
|
||||
__sbit __at 0xDE DMA0INT ; /* DMA0 Operations Complete Flag */
|
||||
__sbit __at 0xDF DMA0EN ; /* DMA0 Enable */
|
||||
|
||||
/* P5 0xD8 */
|
||||
__sbit __at 0xD8 P5_0 ;
|
||||
__sbit __at 0xD9 P5_1 ;
|
||||
__sbit __at 0xDA P5_2 ;
|
||||
__sbit __at 0xDB P5_3 ;
|
||||
__sbit __at 0xDC P5_4 ;
|
||||
__sbit __at 0xDD P5_5 ;
|
||||
__sbit __at 0xDE P5_6 ;
|
||||
__sbit __at 0xDF P5_7 ;
|
||||
|
||||
/* ADC0CN 0xE8 */
|
||||
__sbit __at 0xE9 AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */
|
||||
__sbit __at 0xEA AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */
|
||||
__sbit __at 0xEB AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */
|
||||
__sbit __at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */
|
||||
__sbit __at 0xED AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */
|
||||
__sbit __at 0xEE AD0TM ; /* ADC 0 TRACK MODE */
|
||||
__sbit __at 0xEF AD0EN ; /* ADC 0 ENABLE */
|
||||
|
||||
/* ADC1CN 0xE8 */
|
||||
__sbit __at 0xE9 AD1CM0 ; /* ADC 1 CONVERT START MODE BIT 0 */
|
||||
__sbit __at 0xEA AD1CM1 ; /* ADC 1 CONVERT START MODE BIT 1 */
|
||||
__sbit __at 0xEB AD1CM2 ; /* ADC 1 CONVERT START MODE BIT 1 */
|
||||
__sbit __at 0xEC AD1BUSY ; /* ADC 1 BUSY FLAG */
|
||||
__sbit __at 0xED AD1INT ; /* ADC 1 EOC INTERRUPT FLAG */
|
||||
__sbit __at 0xEE AD1TM ; /* ADC 1 TRACK MODE */
|
||||
__sbit __at 0xEF AD1EN ; /* ADC 1 ENABLE */
|
||||
|
||||
/* ADC2CN 0xE8 */
|
||||
__sbit __at 0xE8 AD2LJST ; /* ADC 2 LEFT JUSTIFY SELECT */
|
||||
__sbit __at 0xE9 AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */
|
||||
__sbit __at 0xEA AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */
|
||||
__sbit __at 0xEB AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */
|
||||
__sbit __at 0xEC AD2BUSY ; /* ADC 2 BUSY FLAG */
|
||||
__sbit __at 0xED AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */
|
||||
__sbit __at 0xEE AD2TM ; /* ADC 2 TRACK MODE */
|
||||
__sbit __at 0xEF AD2EN ; /* ADC 2 ENABLE */
|
||||
|
||||
/* P6 0xE8 */
|
||||
__sbit __at 0xE8 P6_0 ;
|
||||
__sbit __at 0xE9 P6_1 ;
|
||||
__sbit __at 0xEA P6_2 ;
|
||||
__sbit __at 0xEB P6_3 ;
|
||||
__sbit __at 0xEC P6_4 ;
|
||||
__sbit __at 0xED P6_5 ;
|
||||
__sbit __at 0xEE P6_6 ;
|
||||
__sbit __at 0xEF P6_7 ;
|
||||
|
||||
/* SPI0CN 0xF8 */
|
||||
__sbit __at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */
|
||||
__sbit __at 0xF9 TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */
|
||||
__sbit __at 0xFA NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */
|
||||
__sbit __at 0xFB NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */
|
||||
__sbit __at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
|
||||
__sbit __at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */
|
||||
__sbit __at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */
|
||||
__sbit __at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */
|
||||
|
||||
/* CAN0CN 0xF8 */
|
||||
__sbit __at 0xF8 CANINIT ; /* CAN INITIALIZATION */
|
||||
__sbit __at 0xF9 CANIE ; /* CAN MODULE INTERRUPT ENABLE */
|
||||
__sbit __at 0xFA CANSIE ; /* CAN STATUS CHANGE INTERRUPT ENABLE */
|
||||
__sbit __at 0xFB CANEIE ; /* CAN ERROR INTERRUPT ENABLE */
|
||||
__sbit __at 0xFC CANIF ; /* CAN INTERRUPT FLAG */
|
||||
__sbit __at 0xFD CANDAR ; /* CAN DISABLE AUTOMATIC RETRANSMISSION */
|
||||
__sbit __at 0xFE CANCCE ; /* CAN CONFIGURATION CHANGE ENABLE */
|
||||
__sbit __at 0xFF CANTEST ; /* CAN TEST MODE ENABLE */
|
||||
|
||||
/* DMA0CF 0xF8 */
|
||||
__sbit __at 0xF8 DMA0EO ; /* END-OF-OPERATION FLAG */
|
||||
__sbit __at 0xF9 DMA0EOE ; /* END-OF-OPERATION INTERRUPT ENABLE */
|
||||
__sbit __at 0xFA DMA0CI ; /* REPEAT COUNTER OVERFLOW FLAG */
|
||||
__sbit __at 0xFB DMA0CIE ; /* REPEAT COUNTER OVERFLOW INTERRUPT ENABLE */
|
||||
__sbit __at 0xFE DMA0XBY ; /* OFF-CHIP XRAM BUSY FLAG */
|
||||
__sbit __at 0xFF DMA0HLT ; /* HALT DMA0 OFF-CHIP XRAM ACCESS */
|
||||
|
||||
/* P7 0xF8 */
|
||||
__sbit __at 0xF8 P7_0 ;
|
||||
__sbit __at 0xF9 P7_1 ;
|
||||
__sbit __at 0xFA P7_2 ;
|
||||
__sbit __at 0xFB P7_3 ;
|
||||
__sbit __at 0xFC P7_4 ;
|
||||
__sbit __at 0xFD P7_5 ;
|
||||
__sbit __at 0xFE P7_6 ;
|
||||
__sbit __at 0xFF P7_7 ;
|
||||
|
||||
|
||||
/* Predefined SFR Bit Masks */
|
||||
|
||||
#define IDLE 0x01 /* PCON */
|
||||
#define STOP 0x02 /* PCON */
|
||||
#define ECCF 0x01 /* PCA0CPMn */
|
||||
#define PWM 0x02 /* PCA0CPMn */
|
||||
#define TOG 0x04 /* PCA0CPMn */
|
||||
#define MAT 0x08 /* PCA0CPMn */
|
||||
#define CAPN 0x10 /* PCA0CPMn */
|
||||
#define CAPP 0x20 /* PCA0CPMn */
|
||||
#define ECOM 0x40 /* PCA0CPMn */
|
||||
#define PWM16 0x80 /* PCA0CPMn */
|
||||
#define PORSF 0x02 /* RSTSRC */
|
||||
#define SWRSF 0x10 /* RSTSRC */
|
||||
|
||||
|
||||
/* SFR PAGE DEFINITIONS */
|
||||
|
||||
#define CONFIG_PAGE 0x0F /* SYSTEM AND PORT CONFIGURATION PAGE */
|
||||
#define LEGACY_PAGE 0x00 /* LEGACY SFR PAGE */
|
||||
#define TIMER01_PAGE 0x00 /* TIMER 0 AND TIMER 1 */
|
||||
#define CPT0_PAGE 0x01 /* COMPARATOR 0 */
|
||||
#define CPT1_PAGE 0x02 /* COMPARATOR 1 */
|
||||
#define CPT2_PAGE 0x03 /* COMPARATOR 2 */
|
||||
#define UART0_PAGE 0x00 /* UART 0 */
|
||||
#define UART1_PAGE 0x01 /* UART 1 */
|
||||
#define SPI0_PAGE 0x00 /* SPI 0 */
|
||||
#define EMI0_PAGE 0x00 /* EXTERNAL MEMORY INTERFACE */
|
||||
#define ADC0_PAGE 0x00 /* ADC 0 */
|
||||
#define ADC1_PAGE 0x01 /* ADC 1 */
|
||||
#define ADC2_PAGE 0x02 /* ADC 2 */
|
||||
#define SMB0_PAGE 0x00 /* SMBUS 0 */
|
||||
#define TMR2_PAGE 0x00 /* TIMER 2 */
|
||||
#define TMR3_PAGE 0x01 /* TIMER 3 */
|
||||
#define TMR4_PAGE 0x02 /* TIMER 4 */
|
||||
#define DAC0_PAGE 0x00 /* DAC 0 */
|
||||
#define DAC1_PAGE 0x01 /* DAC 1 */
|
||||
#define PCA0_PAGE 0x00 /* PCA 0 */
|
||||
#define DMA0_PAGE 0x03 /* DMA 0 */
|
||||
#define CAN0_PAGE 0x01 /* CAN 0 */
|
||||
|
||||
#endif
|
||||
543
lib/mcs51/C8051F120.h
Normal file
543
lib/mcs51/C8051F120.h
Normal file
@@ -0,0 +1,543 @@
|
||||
/*---------------------------------------------------------------------------
|
||||
C8051F120.h - Register Declarations for the Cygnal/SiLabs C8051F12x-F13x
|
||||
Processor Range
|
||||
|
||||
Copyright (C) 2003, Maarten Brock, sourceforge.brock@dse.nl
|
||||
|
||||
This library is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the
|
||||
Free Software Foundation; either version 2, or (at your option) any
|
||||
later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this library; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
|
||||
MA 02110-1301, USA.
|
||||
|
||||
As a special exception, if you link this library with other files,
|
||||
some of which are compiled with SDCC, to produce an executable,
|
||||
this library does not by itself cause the resulting executable to
|
||||
be covered by the GNU General Public License. This exception does
|
||||
not however invalidate any other reasons why the executable file
|
||||
might be covered by the GNU General Public License.
|
||||
-------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef C8051F120_H
|
||||
#define C8051F120_H
|
||||
|
||||
|
||||
/* BYTE Registers */
|
||||
|
||||
/* All Pages */
|
||||
__sfr __at (0x80) P0 ; /* PORT 0 */
|
||||
__sfr __at (0x81) SP ; /* STACK POINTER */
|
||||
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
|
||||
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
|
||||
__sfr __at (0x84) SFRPAGE ; /* SFR PAGE SELECT */
|
||||
__sfr __at (0x85) SFRNEXT ; /* SFR STACK NEXT PAGE */
|
||||
__sfr __at (0x86) SFRLAST ; /* SFR STACK LAST PAGE */
|
||||
__sfr __at (0x87) PCON ; /* POWER CONTROL */
|
||||
__sfr __at (0x90) P1 ; /* PORT 1 */
|
||||
__sfr __at (0xA0) P2 ; /* PORT 2 */
|
||||
__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
|
||||
__sfr __at (0xB0) P3 ; /* PORT 3 */
|
||||
__sfr __at (0xB1) PSBANK ; /* FLASH BANK SELECT */
|
||||
__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
|
||||
__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
|
||||
__sfr __at (0xE0) ACC ; /* ACCUMULATOR */
|
||||
__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
|
||||
__sfr __at (0xE7) EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
|
||||
__sfr __at (0xF0) B ; /* B REGISTER */
|
||||
__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
|
||||
__sfr __at (0xF7) EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
|
||||
__sfr __at (0xFF) WDTCN ; /* WATCHDOG TIMER CONTROL */
|
||||
|
||||
/* Page 0x00 */
|
||||
__sfr __at (0x88) TCON ; /* TIMER CONTROL */
|
||||
__sfr __at (0x89) TMOD ; /* TIMER MODE */
|
||||
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
|
||||
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
|
||||
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
|
||||
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
|
||||
__sfr __at (0x8E) CKCON ; /* TIMER 0/1 CLOCK CONTROL */
|
||||
__sfr __at (0x8F) PSCTL ; /* FLASH WRITE/ERASE CONTROL */
|
||||
__sfr __at (0x91) SSTA0 ; /* UART 0 STATUS */
|
||||
__sfr __at (0x98) SCON0 ; /* UART 0 CONTROL */
|
||||
__sfr __at (0x98) SCON ; /* UART 0 CONTROL */
|
||||
__sfr __at (0x99) SBUF0 ; /* UART 0 BUFFER */
|
||||
__sfr __at (0x99) SBUF ; /* UART 0 BUFFER */
|
||||
__sfr __at (0x9A) SPI0CFG ; /* SPI 0 CONFIGURATION */
|
||||
__sfr __at (0x9B) SPI0DAT ; /* SPI 0 DATA */
|
||||
__sfr __at (0x9D) SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */
|
||||
__sfr __at (0xA1) EMI0TC ; /* EMIF TIMING CONTROL */
|
||||
__sfr __at (0xA2) EMI0CN ; /* EMIF CONTROL */
|
||||
__sfr __at (0xA2) _XPAGE ; /* XDATA/PDATA PAGE */
|
||||
__sfr __at (0xA3) EMI0CF ; /* EMIF CONFIGURATION */
|
||||
__sfr __at (0xA9) SADDR0 ; /* UART 0 SLAVE ADDRESS */
|
||||
__sfr __at (0xB7) FLSCL ; /* FLASH SCALE */
|
||||
__sfr __at (0xB9) SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */
|
||||
__sfr __at (0xBA) AMX0CF ; /* ADC 0 MUX CONFIGURATION */
|
||||
__sfr __at (0xBB) AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
|
||||
__sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */
|
||||
__sfr __at (0xBE) ADC0L ; /* ADC 0 DATA - LOW BYTE */
|
||||
__sfr __at (0xBF) ADC0H ; /* ADC 0 DATA - HIGH BYTE */
|
||||
__sfr __at (0xC0) SMB0CN ; /* SMBUS 0 CONTROL */
|
||||
__sfr __at (0xC1) SMB0STA ; /* SMBUS 0 STATUS */
|
||||
__sfr __at (0xC2) SMB0DAT ; /* SMBUS 0 DATA */
|
||||
__sfr __at (0xC3) SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
|
||||
__sfr __at (0xC4) ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
|
||||
__sfr __at (0xC5) ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xC6) ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
|
||||
__sfr __at (0xC7) ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xC8) TMR2CN ; /* TIMER 2 CONTROL */
|
||||
__sfr __at (0xC9) TMR2CF ; /* TIMER 2 CONFIGURATION */
|
||||
__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xCC) TMR2L ; /* TIMER 2 - LOW BYTE */
|
||||
__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
|
||||
__sfr __at (0xCD) TMR2H ; /* TIMER 2 - HIGH BYTE */
|
||||
__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
|
||||
__sfr __at (0xCF) SMB0CR ; /* SMBUS 0 CLOCK RATE */
|
||||
__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
|
||||
__sfr __at (0xD2) DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
|
||||
__sfr __at (0xD3) DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xD4) DAC0CN ; /* DAC 0 CONTROL */
|
||||
__sfr __at (0xD8) PCA0CN ; /* PCA 0 COUNTER CONTROL */
|
||||
__sfr __at (0xD9) PCA0MD ; /* PCA 0 COUNTER MODE */
|
||||
__sfr __at (0xDA) PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */
|
||||
__sfr __at (0xDB) PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */
|
||||
__sfr __at (0xDC) PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */
|
||||
__sfr __at (0xDD) PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */
|
||||
__sfr __at (0xDE) PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */
|
||||
__sfr __at (0xDF) PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */
|
||||
__sfr __at (0xE1) PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */
|
||||
__sfr __at (0xE2) PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */
|
||||
__sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */
|
||||
__sfr __at (0xE9) PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */
|
||||
__sfr __at (0xEA) PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */
|
||||
__sfr __at (0xEB) PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */
|
||||
__sfr __at (0xEC) PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */
|
||||
__sfr __at (0xED) PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */
|
||||
__sfr __at (0xEE) PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */
|
||||
__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
|
||||
__sfr __at (0xF8) SPI0CN ; /* SPI 0 CONTROL */
|
||||
__sfr __at (0xF9) PCA0L ; /* PCA 0 TIMER - LOW BYTE */
|
||||
__sfr __at (0xFA) PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
|
||||
__sfr __at (0xFB) PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */
|
||||
__sfr __at (0xFC) PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */
|
||||
__sfr __at (0xFD) PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */
|
||||
__sfr __at (0xFE) PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */
|
||||
|
||||
/* Page 0x01 */
|
||||
__sfr __at (0x88) CPT0CN ; /* COMPARATOR 0 CONTROL */
|
||||
__sfr __at (0x89) CPT0MD ; /* COMPARATOR 0 CONFIGURATION */
|
||||
__sfr __at (0x98) SCON1 ; /* UART 1 CONTROL */
|
||||
__sfr __at (0x99) SBUF1 ; /* UART 1 BUFFER */
|
||||
__sfr __at (0xC8) TMR3CN ; /* TIMER 3 CONTROL */
|
||||
__sfr __at (0xC9) TMR3CF ; /* TIMER 3 CONFIGURATION */
|
||||
__sfr __at (0xCA) RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at (0xCB) RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xCC) TMR3L ; /* TIMER 3 - LOW BYTE */
|
||||
__sfr __at (0xCD) TMR3H ; /* TIMER 3 - HIGH BYTE */
|
||||
__sfr __at (0xD2) DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
|
||||
__sfr __at (0xD3) DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xD4) DAC1CN ; /* DAC 1 CONTROL */
|
||||
|
||||
/* Page 0x02 */
|
||||
__sfr __at (0x88) CPT1CN ; /* COMPARATOR 1 CONTROL */
|
||||
__sfr __at (0x89) CPT1MD ; /* COMPARATOR 1 CONFIGURATION */
|
||||
__sfr __at (0xBA) AMX2CF ; /* ADC 2 MUX CONFIGURATION */
|
||||
__sfr __at (0xBB) AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */
|
||||
__sfr __at (0xBC) ADC2CF ; /* ADC 2 CONFIGURATION */
|
||||
__sfr __at (0xBE) ADC2 ; /* ADC 2 DATA */
|
||||
__sfr __at (0xC4) ADC2GT ; /* ADC 2 GREATER-THAN REGISTER */
|
||||
__sfr __at (0xC6) ADC2LT ; /* ADC 2 LESS-THAN REGISTER */
|
||||
__sfr __at (0xC8) TMR4CN ; /* TIMER 4 CONTROL */
|
||||
__sfr __at (0xC9) TMR4CF ; /* TIMER 4 CONFIGURATION */
|
||||
__sfr __at (0xCA) RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at (0xCB) RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xCC) TMR4L ; /* TIMER 4 - LOW BYTE */
|
||||
__sfr __at (0xCD) TMR4H ; /* TIMER 4 - HIGH BYTE */
|
||||
__sfr __at (0xE8) ADC2CN ; /* ADC 2 CONTROL */
|
||||
|
||||
/* Page 0x03 */
|
||||
__sfr __at (0x91) MAC0BL ; /* MAC0 B Register Low Byte */
|
||||
__sfr __at (0x92) MAC0BH ; /* MAC0 B Register High Byte */
|
||||
__sfr __at (0x93) MAC0ACC0 ; /* MAC0 Accumulator Byte 0 (LSB) */
|
||||
__sfr __at (0x94) MAC0ACC1 ; /* MAC0 Accumulator Byte 1 */
|
||||
__sfr __at (0x95) MAC0ACC2 ; /* MAC0 Accumulator Byte 2 */
|
||||
__sfr __at (0x96) MAC0ACC3 ; /* MAC0 Accumulator Byte 3 (MSB) */
|
||||
__sfr __at (0x97) MAC0OVR ; /* MAC0 Accumulator Overflow */
|
||||
__sfr __at (0xC0) MAC0STA ; /* MAC0 Status Register */
|
||||
__sfr __at (0xC1) MAC0AL ; /* MAC0 A Register Low Byte */
|
||||
__sfr __at (0xC2) MAC0AH ; /* MAC0 A Register High Byte */
|
||||
__sfr __at (0xC3) MAC0CF ; /* MAC0 Configuration */
|
||||
__sfr __at (0xCE) MAC0RNDL ; /* MAC0 Rounding Register Low Byte */
|
||||
__sfr __at (0xCF) MAC0RNDH ; /* MAC0 Rounding Register High Byte */
|
||||
|
||||
/* Page 0x0F */
|
||||
__sfr __at (0x88) FLSTAT ; /* FLASH STATUS */
|
||||
__sfr __at (0x89) PLL0CN ; /* PLL 0 CONTROL */
|
||||
__sfr __at (0x8A) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at (0x8B) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
|
||||
__sfr __at (0x8C) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at (0x8D) PLL0DIV ; /* PLL 0 DIVIDER */
|
||||
__sfr __at (0x8E) PLL0MUL ; /* PLL 0 MULTIPLIER */
|
||||
__sfr __at (0x8F) PLL0FLT ; /* PLL 0 FILTER */
|
||||
__sfr __at (0x96) SFRPGCN ; /* SFR PAGE CONTROL */
|
||||
__sfr __at (0x97) CLKSEL ; /* SYSTEM CLOCK SELECT */
|
||||
__sfr __at (0x9A) CCH0MA ; /* CACHE MISS ACCUMULATOR */
|
||||
__sfr __at (0x9C) P4MDOUT ; /* PORT 4 OUTPUT MODE */
|
||||
__sfr __at (0x9D) P5MDOUT ; /* PORT 5 OUTPUT MODE */
|
||||
__sfr __at (0x9E) P6MDOUT ; /* PORT 6 OUTPUT MODE */
|
||||
__sfr __at (0x9F) P7MDOUT ; /* PORT 7 OUTPUT MODE */
|
||||
__sfr __at (0xA1) CCH0CN ; /* CACHE CONTROL */
|
||||
__sfr __at (0xA2) CCH0TN ; /* CACHE TUNING REGISTER */
|
||||
__sfr __at (0xA3) CCH0LC ; /* CACHE LOCK */
|
||||
__sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE */
|
||||
__sfr __at (0xA5) P1MDOUT ; /* PORT 1 OUTPUT MODE */
|
||||
__sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA7) P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xAD) P1MDIN ; /* PORT 1 INPUT MODE */
|
||||
__sfr __at (0xB7) FLACL ; /* FLASH ACCESS LIMIT */
|
||||
__sfr __at (0xC8) P4 ; /* PORT 4 */
|
||||
__sfr __at (0xD8) P5 ; /* PORT 5 */
|
||||
__sfr __at (0xE1) XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */
|
||||
__sfr __at (0xE2) XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */
|
||||
__sfr __at (0xE3) XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */
|
||||
__sfr __at (0xE8) P6 ; /* PORT 6 */
|
||||
__sfr __at (0xF8) P7 ; /* PORT 7 */
|
||||
|
||||
|
||||
/* WORD/DWORD Registers */
|
||||
|
||||
/* Page 0x00 */
|
||||
__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
|
||||
__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
|
||||
__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
|
||||
__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
|
||||
__sfr16 __at (0xBFBE) ADC0 ; /* ADC 0 DATA WORD */
|
||||
__sfr16 __at (0xC5C4) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */
|
||||
__sfr16 __at (0xC7C6) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */
|
||||
__sfr16 __at (0xD3D2) DAC0 ; /* DAC 0 REGISTER WORD */
|
||||
__sfr16 __at (0xFAF9) PCA0 ; /* PCA 0 TIMER COUNTER */
|
||||
__sfr16 __at (0xFCFB) PCA0CP0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE WORD */
|
||||
__sfr16 __at (0xFEFD) PCA0CP1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE WORD */
|
||||
__sfr16 __at (0xEAE9) PCA0CP2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE WORD */
|
||||
__sfr16 __at (0xECEB) PCA0CP3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE WORD */
|
||||
__sfr16 __at (0xEEED) PCA0CP4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE WORD */
|
||||
__sfr16 __at (0xE2E1) PCA0CP5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE WORD */
|
||||
|
||||
/* Page 0x01 */
|
||||
__sfr16 __at (0xCDCC) TMR3 ; /* TIMER 3 COUNTER */
|
||||
__sfr16 __at (0xCBCA) RCAP3 ; /* TIMER 3 CAPTURE REGISTER WORD */
|
||||
__sfr16 __at (0xD3D2) DAC1 ; /* DAC 1 REGISTER WORD */
|
||||
|
||||
/* Page 0x02 */
|
||||
__sfr16 __at (0xCDCC) TMR4 ; /* TIMER 4 COUNTER */
|
||||
__sfr16 __at (0xCBCA) RCAP4 ; /* TIMER 4 CAPTURE REGISTER WORD */
|
||||
|
||||
/* Page 0x03 */
|
||||
__sfr16 __at (0xC2C1) MAC0A ; /* MAC0 A Register */
|
||||
/* No sfr16 definition for MAC0B because MAC0BL must be written last */
|
||||
__sfr32 __at (0x96959493) MAC0ACC ; /* MAC0 Accumulator */
|
||||
__sfr16 __at (0xCFCE) MAC0RND ; /* MAC0 Rounding Register */
|
||||
|
||||
|
||||
/* BIT Registers */
|
||||
|
||||
/* P0 0x80 */
|
||||
__sbit __at (0x80) P0_0 ;
|
||||
__sbit __at (0x81) P0_1 ;
|
||||
__sbit __at (0x82) P0_2 ;
|
||||
__sbit __at (0x83) P0_3 ;
|
||||
__sbit __at (0x84) P0_4 ;
|
||||
__sbit __at (0x85) P0_5 ;
|
||||
__sbit __at (0x86) P0_6 ;
|
||||
__sbit __at (0x87) P0_7 ;
|
||||
|
||||
/* TCON 0x88 */
|
||||
__sbit __at (0x88) IT0 ; /* EXT. INTERRUPT 0 TYPE */
|
||||
__sbit __at (0x89) IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
|
||||
__sbit __at (0x8A) IT1 ; /* EXT. INTERRUPT 1 TYPE */
|
||||
__sbit __at (0x8B) IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
|
||||
__sbit __at (0x8C) TR0 ; /* TIMER 0 ON/OFF CONTROL */
|
||||
__sbit __at (0x8D) TF0 ; /* TIMER 0 OVERFLOW FLAG */
|
||||
__sbit __at (0x8E) TR1 ; /* TIMER 1 ON/OFF CONTROL */
|
||||
__sbit __at (0x8F) TF1 ; /* TIMER 1 OVERFLOW FLAG */
|
||||
|
||||
/* CPT0CN 0x88 */
|
||||
__sbit __at (0x88) CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */
|
||||
__sbit __at (0x89) CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */
|
||||
__sbit __at (0x8A) CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */
|
||||
__sbit __at (0x8B) CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */
|
||||
__sbit __at (0x8C) CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */
|
||||
__sbit __at (0x8D) CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */
|
||||
__sbit __at (0x8E) CP0OUT ; /* COMPARATOR 0 OUTPUT */
|
||||
__sbit __at (0x8F) CP0EN ; /* COMPARATOR 0 ENABLE */
|
||||
|
||||
/* CPT1CN 0x88 */
|
||||
__sbit __at (0x88) CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */
|
||||
__sbit __at (0x89) CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */
|
||||
__sbit __at (0x8A) CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */
|
||||
__sbit __at (0x8B) CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */
|
||||
__sbit __at (0x8C) CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */
|
||||
__sbit __at (0x8D) CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */
|
||||
__sbit __at (0x8E) CP1OUT ; /* COMPARATOR 1 OUTPUT */
|
||||
__sbit __at (0x8F) CP1EN ; /* COMPARATOR 1 ENABLE */
|
||||
|
||||
/* FLSTAT 0x88 */
|
||||
__sbit __at (0x88) FLHBUSY ; /* FLASH BUSY */
|
||||
|
||||
/* P1 0x90 */
|
||||
__sbit __at (0x90) P1_0 ;
|
||||
__sbit __at (0x91) P1_1 ;
|
||||
__sbit __at (0x92) P1_2 ;
|
||||
__sbit __at (0x93) P1_3 ;
|
||||
__sbit __at (0x94) P1_4 ;
|
||||
__sbit __at (0x95) P1_5 ;
|
||||
__sbit __at (0x96) P1_6 ;
|
||||
__sbit __at (0x97) P1_7 ;
|
||||
|
||||
/* SCON0 0x98 */
|
||||
__sbit __at (0x98) RI0 ; /* UART 0 RX INTERRUPT FLAG */
|
||||
__sbit __at (0x98) RI ; /* UART 0 RX INTERRUPT FLAG */
|
||||
__sbit __at (0x99) TI0 ; /* UART 0 TX INTERRUPT FLAG */
|
||||
__sbit __at (0x99) TI ; /* UART 0 TX INTERRUPT FLAG */
|
||||
__sbit __at (0x9A) RB80 ; /* UART 0 RX BIT 8 */
|
||||
__sbit __at (0x9B) TB80 ; /* UART 0 TX BIT 8 */
|
||||
__sbit __at (0x9C) REN0 ; /* UART 0 RX ENABLE */
|
||||
__sbit __at (0x9C) REN ; /* UART 0 RX ENABLE */
|
||||
__sbit __at (0x9D) SM20 ; /* UART 0 MULTIPROCESSOR EN */
|
||||
__sbit __at (0x9E) SM10 ; /* UART 0 MODE 1 */
|
||||
__sbit __at (0x9F) SM00 ; /* UART 0 MODE 0 */
|
||||
|
||||
/* SCON1 0x98 */
|
||||
__sbit __at (0x98) RI1 ; /* UART 1 RX INTERRUPT FLAG */
|
||||
__sbit __at (0x99) TI1 ; /* UART 1 TX INTERRUPT FLAG */
|
||||
__sbit __at (0x9A) RB81 ; /* UART 1 RX BIT 8 */
|
||||
__sbit __at (0x9B) TB81 ; /* UART 1 TX BIT 8 */
|
||||
__sbit __at (0x9C) REN1 ; /* UART 1 RX ENABLE */
|
||||
__sbit __at (0x9D) MCE1 ; /* UART 1 MCE */
|
||||
__sbit __at (0x9F) S1MODE ; /* UART 1 MODE */
|
||||
|
||||
/* P2 0xA0 */
|
||||
__sbit __at (0xA0) P2_0 ;
|
||||
__sbit __at (0xA1) P2_1 ;
|
||||
__sbit __at (0xA2) P2_2 ;
|
||||
__sbit __at (0xA3) P2_3 ;
|
||||
__sbit __at (0xA4) P2_4 ;
|
||||
__sbit __at (0xA5) P2_5 ;
|
||||
__sbit __at (0xA6) P2_6 ;
|
||||
__sbit __at (0xA7) P2_7 ;
|
||||
|
||||
/* IE 0xA8 */
|
||||
__sbit __at (0xA8) EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
|
||||
__sbit __at (0xA9) ET0 ; /* TIMER 0 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAA) EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
|
||||
__sbit __at (0xAB) ET1 ; /* TIMER 1 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAC) ES0 ; /* UART0 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAC) ES ; /* UART0 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAD) ET2 ; /* TIMER 2 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAF) EA ; /* GLOBAL INTERRUPT ENABLE */
|
||||
|
||||
/* P3 0xB0 */
|
||||
__sbit __at (0xB0) P3_0 ;
|
||||
__sbit __at (0xB1) P3_1 ;
|
||||
__sbit __at (0xB2) P3_2 ;
|
||||
__sbit __at (0xB3) P3_3 ;
|
||||
__sbit __at (0xB4) P3_4 ;
|
||||
__sbit __at (0xB5) P3_5 ;
|
||||
__sbit __at (0xB6) P3_6 ;
|
||||
__sbit __at (0xB7) P3_7 ;
|
||||
|
||||
/* IP 0xB8 */
|
||||
__sbit __at (0xB8) PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
|
||||
__sbit __at (0xB9) PT0 ; /* TIMER 0 PRIORITY */
|
||||
__sbit __at (0xBA) PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
|
||||
__sbit __at (0xBB) PT1 ; /* TIMER 1 PRIORITY */
|
||||
__sbit __at (0xBC) PS0 ; /* SERIAL PORT PRIORITY */
|
||||
__sbit __at (0xBC) PS ; /* SERIAL PORT PRIORITY */
|
||||
__sbit __at (0xBD) PT2 ; /* TIMER 2 PRIORITY */
|
||||
|
||||
/* SMB0CN 0xC0 */
|
||||
__sbit __at (0xC0) SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
|
||||
__sbit __at (0xC1) SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
|
||||
__sbit __at (0xC2) AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
|
||||
__sbit __at (0xC3) SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
|
||||
__sbit __at (0xC4) STO ; /* SMBUS 0 STOP FLAG */
|
||||
__sbit __at (0xC5) STA ; /* SMBUS 0 START FLAG */
|
||||
__sbit __at (0xC6) ENSMB ; /* SMBUS 0 ENABLE */
|
||||
__sbit __at (0xC7) BUSY ; /* SMBUS 0 BUSY */
|
||||
|
||||
/* MAC0STA 0xC0 */
|
||||
__sbit __at (0xC0) MAC0N ; /* MAC 0 NEGATIVE FLAG */
|
||||
__sbit __at (0xC1) MAC0SO ; /* MAC 0 SOFT OVERFLOW FLAG */
|
||||
__sbit __at (0xC2) MAC0Z ; /* MAC 0 ZERO FLAG */
|
||||
__sbit __at (0xC3) MAC0HO ; /* MAC 0 HARD OVERFLOW FLAG */
|
||||
|
||||
/* TMR2CN 0xC8 */
|
||||
__sbit __at (0xC8) CPRL2 ; /* TIMER 2 CAPTURE SELECT */
|
||||
__sbit __at (0xC9) CT2 ; /* TIMER 2 COUNTER SELECT */
|
||||
__sbit __at (0xCA) TR2 ; /* TIMER 2 ON/OFF CONTROL */
|
||||
__sbit __at (0xCB) EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
|
||||
__sbit __at (0xCE) EXF2 ; /* TIMER 2 EXTERNAL FLAG */
|
||||
__sbit __at (0xCF) TF2 ; /* TIMER 2 OVERFLOW FLAG */
|
||||
|
||||
/* TMR3CN 0xC8 */
|
||||
__sbit __at (0xC8) CPRL3 ; /* TIMER 3 CAPTURE SELECT */
|
||||
__sbit __at (0xC9) CT3 ; /* TIMER 3 COUNTER SELECT */
|
||||
__sbit __at (0xCA) TR3 ; /* TIMER 3 ON/OFF CONTROL */
|
||||
__sbit __at (0xCB) EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */
|
||||
__sbit __at (0xCE) EXF3 ; /* TIMER 3 EXTERNAL FLAG */
|
||||
__sbit __at (0xCF) TF3 ; /* TIMER 3 OVERFLOW FLAG */
|
||||
|
||||
/* TMR4CN 0xC8 */
|
||||
__sbit __at (0xC8) CPRL4 ; /* TIMER 4 CAPTURE SELECT */
|
||||
__sbit __at (0xC9) CT4 ; /* TIMER 4 COUNTER SELECT */
|
||||
__sbit __at (0xCA) TR4 ; /* TIMER 4 ON/OFF CONTROL */
|
||||
__sbit __at (0xCB) EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */
|
||||
__sbit __at (0xCE) EXF4 ; /* TIMER 4 EXTERNAL FLAG */
|
||||
__sbit __at (0xCF) TF4 ; /* TIMER 4 OVERFLOW FLAG */
|
||||
|
||||
/* P4 0xC8 */
|
||||
__sbit __at (0xC8) P4_0 ;
|
||||
__sbit __at (0xC9) P4_1 ;
|
||||
__sbit __at (0xCA) P4_2 ;
|
||||
__sbit __at (0xCB) P4_3 ;
|
||||
__sbit __at (0xCC) P4_4 ;
|
||||
__sbit __at (0xCD) P4_5 ;
|
||||
__sbit __at (0xCE) P4_6 ;
|
||||
__sbit __at (0xCF) P4_7 ;
|
||||
|
||||
/* PSW 0xD0 */
|
||||
__sbit __at (0xD0) P ; /* ACCUMULATOR PARITY FLAG */
|
||||
__sbit __at (0xD1) F1 ; /* USER FLAG 1 */
|
||||
__sbit __at (0xD2) OV ; /* OVERFLOW FLAG */
|
||||
__sbit __at (0xD3) RS0 ; /* REGISTER BANK SELECT 0 */
|
||||
__sbit __at (0xD4) RS1 ; /* REGISTER BANK SELECT 1 */
|
||||
__sbit __at (0xD5) F0 ; /* USER FLAG 0 */
|
||||
__sbit __at (0xD6) AC ; /* AUXILIARY CARRY FLAG */
|
||||
__sbit __at (0xD7) CY ; /* CARRY FLAG */
|
||||
|
||||
/* PCA0CN D8H */
|
||||
__sbit __at (0xD8) CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
|
||||
__sbit __at (0xD9) CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
|
||||
__sbit __at (0xDA) CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
|
||||
__sbit __at (0xDB) CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
|
||||
__sbit __at (0xDC) CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
|
||||
__sbit __at (0xDD) CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */
|
||||
__sbit __at (0xDE) CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
|
||||
__sbit __at (0xDF) CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
|
||||
|
||||
/* P5 0xD8 */
|
||||
__sbit __at (0xD8) P5_0 ;
|
||||
__sbit __at (0xD9) P5_1 ;
|
||||
__sbit __at (0xDA) P5_2 ;
|
||||
__sbit __at (0xDB) P5_3 ;
|
||||
__sbit __at (0xDC) P5_4 ;
|
||||
__sbit __at (0xDD) P5_5 ;
|
||||
__sbit __at (0xDE) P5_6 ;
|
||||
__sbit __at (0xDF) P5_7 ;
|
||||
|
||||
/* ADC0CN E8H */
|
||||
__sbit __at (0xE8) AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
|
||||
__sbit __at (0xE9) AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */
|
||||
__sbit __at (0xEA) AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */
|
||||
__sbit __at (0xEB) AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */
|
||||
__sbit __at (0xEC) AD0BUSY ; /* ADC 0 BUSY FLAG */
|
||||
__sbit __at (0xED) AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */
|
||||
__sbit __at (0xEE) AD0TM ; /* ADC 0 TRACK MODE */
|
||||
__sbit __at (0xEF) AD0EN ; /* ADC 0 ENABLE */
|
||||
|
||||
/* ADC2CN E8H */
|
||||
__sbit __at (0xE8) AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */
|
||||
__sbit __at (0xE9) AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */
|
||||
__sbit __at (0xEA) AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */
|
||||
__sbit __at (0xEB) AD2CM2 ; /* ADC 2 CONVERT START MODE BIT 2 */
|
||||
__sbit __at (0xEC) AD2BUSY ; /* ADC 2 BUSY FLAG */
|
||||
__sbit __at (0xED) AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */
|
||||
__sbit __at (0xEE) AD2TM ; /* ADC 2 TRACK MODE */
|
||||
__sbit __at (0xEF) AD2EN ; /* ADC 2 ENABLE */
|
||||
|
||||
/* P6 0xE8 */
|
||||
__sbit __at (0xE8) P6_0 ;
|
||||
__sbit __at (0xE9) P6_1 ;
|
||||
__sbit __at (0xEA) P6_2 ;
|
||||
__sbit __at (0xEB) P6_3 ;
|
||||
__sbit __at (0xEC) P6_4 ;
|
||||
__sbit __at (0xED) P6_5 ;
|
||||
__sbit __at (0xEE) P6_6 ;
|
||||
__sbit __at (0xEF) P6_7 ;
|
||||
|
||||
/* SPI0CN F8H */
|
||||
__sbit __at (0xF8) SPIEN ; /* SPI 0 SPI ENABLE */
|
||||
__sbit __at (0xF9) TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */
|
||||
__sbit __at (0xFA) NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */
|
||||
__sbit __at (0xFB) NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */
|
||||
__sbit __at (0xFC) RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
|
||||
__sbit __at (0xFD) MODF ; /* SPI 0 MODE FAULT FLAG */
|
||||
__sbit __at (0xFE) WCOL ; /* SPI 0 WRITE COLLISION FLAG */
|
||||
__sbit __at (0xFF) SPIF ; /* SPI 0 INTERRUPT FLAG */
|
||||
|
||||
/* P7 0xF8 */
|
||||
__sbit __at (0xF8) P7_0 ;
|
||||
__sbit __at (0xF9) P7_1 ;
|
||||
__sbit __at (0xFA) P7_2 ;
|
||||
__sbit __at (0xFB) P7_3 ;
|
||||
__sbit __at (0xFC) P7_4 ;
|
||||
__sbit __at (0xFD) P7_5 ;
|
||||
__sbit __at (0xFE) P7_6 ;
|
||||
__sbit __at (0xFF) P7_7 ;
|
||||
|
||||
|
||||
/* Predefined SFR Bit Masks */
|
||||
|
||||
#define PCON_IDLE 0x01 /* PCON */
|
||||
#define PCON_STOP 0x02 /* PCON */
|
||||
#define ECCF 0x01 /* PCA0CPMn */
|
||||
#define PWM 0x02 /* PCA0CPMn */
|
||||
#define TOG 0x04 /* PCA0CPMn */
|
||||
#define MAT 0x08 /* PCA0CPMn */
|
||||
#define CAPN 0x10 /* PCA0CPMn */
|
||||
#define CAPP 0x20 /* PCA0CPMn */
|
||||
#define ECOM 0x40 /* PCA0CPMn */
|
||||
#define PWM16 0x80 /* PCA0CPMn */
|
||||
#define PINRSF 0x01 /* RSTSRC */
|
||||
#define PORSF 0x02 /* RSTSRC */
|
||||
#define MCDRSF 0x04 /* RSTSRC */
|
||||
#define WDTRSF 0x08 /* RSTSRC */
|
||||
#define SWRSF 0x10 /* RSTSRC */
|
||||
#define C0RSEF 0x20 /* RSTSRC */
|
||||
#define CNVRSEF 0x40 /* RSTSRC */
|
||||
|
||||
|
||||
/* SFR PAGE DEFINITIONS */
|
||||
|
||||
#define CONFIG_PAGE 0x0F /* SYSTEM AND PORT CONFIGURATION PAGE */
|
||||
#define LEGACY_PAGE 0x00 /* LEGACY SFR PAGE */
|
||||
#define TIMER01_PAGE 0x00 /* TIMER 0 AND TIMER 1 */
|
||||
#define CPT0_PAGE 0x01 /* COMPARATOR 0 */
|
||||
#define CPT1_PAGE 0x02 /* COMPARATOR 1 */
|
||||
#define UART0_PAGE 0x00 /* UART 0 */
|
||||
#define UART1_PAGE 0x01 /* UART 1 */
|
||||
#define SPI0_PAGE 0x00 /* SPI 0 */
|
||||
#define EMI0_PAGE 0x00 /* EXTERNAL MEMORY INTERFACE */
|
||||
#define ADC0_PAGE 0x00 /* ADC 0 */
|
||||
#define ADC2_PAGE 0x02 /* ADC 2 */
|
||||
#define SMB0_PAGE 0x00 /* SMBUS 0 */
|
||||
#define TMR2_PAGE 0x00 /* TIMER 2 */
|
||||
#define TMR3_PAGE 0x01 /* TIMER 3 */
|
||||
#define TMR4_PAGE 0x02 /* TIMER 4 */
|
||||
#define DAC0_PAGE 0x00 /* DAC 0 */
|
||||
#define DAC1_PAGE 0x01 /* DAC 1 */
|
||||
#define PCA0_PAGE 0x00 /* PCA 0 */
|
||||
#define PLL0_PAGE 0x0F /* PLL 0 */
|
||||
#define MAC0_PAGE 0x03 /* MULTIPLY / ACCUMULATE 0 */
|
||||
|
||||
#endif
|
||||
239
lib/mcs51/C8051F200.h
Normal file
239
lib/mcs51/C8051F200.h
Normal file
@@ -0,0 +1,239 @@
|
||||
/*---------------------------------------------------------------------------
|
||||
C8051F200.h - Register Declarations for the Cygnal/SiLabs C8051F2xx
|
||||
Processor Range
|
||||
|
||||
Copyright (C) 2006, Maarten Brock, sourceforge.brock@dse.nl
|
||||
|
||||
This library is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the
|
||||
Free Software Foundation; either version 2, or (at your option) any
|
||||
later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this library; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
|
||||
MA 02110-1301, USA.
|
||||
|
||||
As a special exception, if you link this library with other files,
|
||||
some of which are compiled with SDCC, to produce an executable,
|
||||
this library does not by itself cause the resulting executable to
|
||||
be covered by the GNU General Public License. This exception does
|
||||
not however invalidate any other reasons why the executable file
|
||||
might be covered by the GNU General Public License.
|
||||
-------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef C8051F200_H
|
||||
#define C8051F200_H
|
||||
|
||||
|
||||
/* BYTE Registers */
|
||||
__sfr __at (0x80) P0 ; /* PORT 0 */
|
||||
__sfr __at (0x81) SP ; /* STACK POINTER */
|
||||
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
|
||||
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
|
||||
__sfr __at (0x87) PCON ; /* POWER Control */
|
||||
__sfr __at (0x88) TCON ; /* TIMER Control */
|
||||
__sfr __at (0x89) TMOD ; /* TIMER MODE */
|
||||
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
|
||||
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
|
||||
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
|
||||
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
|
||||
__sfr __at (0x8E) CKCON ; /* CLOCK Control */
|
||||
__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W Control */
|
||||
__sfr __at (0x90) P1 ; /* PORT 1 */
|
||||
__sfr __at (0x98) SCON ; /* SERIAL PORT Control */
|
||||
__sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
|
||||
__sfr __at (0x9A) SPI0CFG ; /* SERIAL PERIPHERAL INTERFACE 0 Configuration */
|
||||
__sfr __at (0x9B) SPI0DAT ; /* SERIAL PERIPHERAL INTERFACE 0 DATA */
|
||||
__sfr __at (0x9D) SPI0CKR ; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE Control */
|
||||
__sfr __at (0x9E) CPT0CN ; /* COMPARATOR 0 Control */
|
||||
__sfr __at (0x9F) CPT1CN ; /* COMPARATOR 1 Control */
|
||||
__sfr __at (0xA0) P2 ; /* PORT 2 */
|
||||
__sfr __at (0xA4) PRT0CF ; /* PORT 0 OUTPUT MODE Configuration */
|
||||
__sfr __at (0xA5) PRT1CF ; /* PORT 1 OUTPUT MODE Configuration */
|
||||
__sfr __at (0xA6) PRT2CF ; /* PORT 2 OUTPUT MODE Configuration */
|
||||
__sfr __at (0xA7) PRT3CF ; /* PORT 3 OUTPUT MODE Configuration */
|
||||
__sfr __at (0xA8) IE ; /* Interrupt Enable */
|
||||
__sfr __at (0xAD) SWCINT ; /* SOFTWARE-Controlled Interrupt FLAGS */
|
||||
__sfr __at (0xAD) PRT1IF ; /* SOFTWARE-Controlled Interrupt FLAGS (LEGACY NAME) */
|
||||
__sfr __at (0xAF) EMI0CN ; /* EXTERNAL MEMORY INTERFACE Control (F206/F226/F236)*/
|
||||
__sfr __at (0xAF) _XPAGE ; /* XDATA/PDATA PAGE */
|
||||
__sfr __at (0xB0) P3 ; /* PORT 3 */
|
||||
__sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR Control */
|
||||
__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR Control */
|
||||
__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
|
||||
__sfr __at (0xB7) FLACL ; /* FLASH ACESS LIMIT */
|
||||
__sfr __at (0xB8) IP ; /* Interrupt Priority */
|
||||
__sfr __at (0xBB) AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION (Not on F230/1/6) */
|
||||
__sfr __at (0xBC) ADC0CF ; /* ADC 0 Configuration (Not on F230/1/6) */
|
||||
__sfr __at (0xBE) ADC0L ; /* ADC 0 Data LOW ( F206 only ) */
|
||||
__sfr __at (0xBF) ADC0H ; /* ADC 0 Data High */
|
||||
__sfr __at (0xC4) ADC0GTL ; /* ADC 0 GREATER-THAN Register LOW( F206 only ) */
|
||||
__sfr __at (0xC5) ADC0GTH ; /* ADC 0 GREATER-THAN Register (Not on F230/1/6) */
|
||||
__sfr __at (0xC6) ADC0LTL ; /* ADC 0 LESS-THAN Register LOW ( F206 only ) */
|
||||
__sfr __at (0xC7) ADC0LTH ; /* ADC 0 LESS-THAN Register (Not on F230/1/6) */
|
||||
__sfr __at (0xC8) T2CON ; /* TIMER 2 Control */
|
||||
__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE Register - LOW BYTE */
|
||||
__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE Register - HIGH BYTE */
|
||||
__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
|
||||
__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
|
||||
__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
|
||||
__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 Control */
|
||||
__sfr __at (0xE0) ACC ; /* ACCUMULATOR */
|
||||
__sfr __at (0xE1) PRT0MX ; /* PORT MUX Configuration Register 0 */
|
||||
__sfr __at (0xE2) PRT1MX ; /* PORT MUX Configuration Register 1 */
|
||||
__sfr __at (0xE3) PRT2MX ; /* PORT MUX Configuration Register 2 */
|
||||
__sfr __at (0xE6) EIE1 ; /* EXTERNAL Interrupt Enable 1 */
|
||||
__sfr __at (0xE7) EIE2 ; /* EXTERNAL Interrupt Enable 2 */
|
||||
__sfr __at (0xE8) ADC0CN ; /* ADC 0 Control (Not on F230/1/6) */
|
||||
__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
|
||||
__sfr __at (0xF0) B ; /* B Register */
|
||||
__sfr __at (0xF1) P0MODE ; /* PORT 0 INPUT MODE Configuration */
|
||||
__sfr __at (0xF2) P1MODE ; /* PORT 1 INPUT MODE Configuration */
|
||||
__sfr __at (0xF3) P2MODE ; /* PORT 2 INPUT MODE Configuration */
|
||||
__sfr __at (0xF4) P3MODE ; /* PORT 3 INPUT MODE Configuration (Not on F221/F231)*/
|
||||
__sfr __at (0xF6) EIP1 ; /* EXTERNAL Interrupt Priority Register 1 */
|
||||
__sfr __at (0xF7) EIP2 ; /* EXTERNAL Interrupt Priority Register 2 */
|
||||
__sfr __at (0xF8) SPI0CN ; /* SERIAL PERIPHERAL INTERFACE 0 Control */
|
||||
__sfr __at (0xFF) WDTCN ; /* WATCHDOG TIMER Control */
|
||||
|
||||
|
||||
/* WORD/DWORD Registers */
|
||||
|
||||
__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
|
||||
__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
|
||||
__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
|
||||
__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
|
||||
__sfr16 __at (0xBFBE) ADC0 ; /* ADC 0 DATA WORD */
|
||||
__sfr16 __at (0xC5C4) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */
|
||||
__sfr16 __at (0xC7C6) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */
|
||||
|
||||
|
||||
/* BIT Registers */
|
||||
|
||||
/* P0 0x80 */
|
||||
__sbit __at (0x80) P0_0 ;
|
||||
__sbit __at (0x81) P0_1 ;
|
||||
__sbit __at (0x82) P0_2 ;
|
||||
__sbit __at (0x83) P0_3 ;
|
||||
__sbit __at (0x84) P0_4 ; /* Port0 I/O Bits */
|
||||
__sbit __at (0x85) P0_5 ;
|
||||
__sbit __at (0x86) P0_6 ;
|
||||
__sbit __at (0x87) P0_7 ;
|
||||
|
||||
/* TCON 0x88 */
|
||||
__sbit __at (0x88) IT0 ; /* EXT. Interrupt 0 TYPE */
|
||||
__sbit __at (0x89) IE0 ; /* EXT. Interrupt 0 EDGE FLAG */
|
||||
__sbit __at (0x8A) IT1 ; /* EXT. Interrupt 1 TYPE */
|
||||
__sbit __at (0x8B) IE1 ; /* EXT. Interrupt 1 EDGE FLAG */
|
||||
__sbit __at (0x8C) TR0 ; /* TIMER 0 ON/OFF Control */
|
||||
__sbit __at (0x8D) TF0 ; /* TIMER 0 Overflow FLAG */
|
||||
__sbit __at (0x8E) TR1 ; /* TIMER 1 ON/OFF Control */
|
||||
__sbit __at (0x8F) TF1 ; /* TIMER 1 Overflow FLAG */
|
||||
|
||||
/* P1 0x90 */
|
||||
__sbit __at (0x90) P1_0 ;
|
||||
__sbit __at (0x91) P1_1 ;
|
||||
__sbit __at (0x92) P1_2 ;
|
||||
__sbit __at (0x93) P1_3 ;
|
||||
__sbit __at (0x94) P1_4 ; /* Port1 I/O Bits */
|
||||
__sbit __at (0x95) P1_5 ;
|
||||
__sbit __at (0x96) P1_6 ;
|
||||
__sbit __at (0x97) P1_7 ;
|
||||
|
||||
/* SCON 0x98 */
|
||||
__sbit __at (0x98) RI ; /* RECEIVE Interrupt FLAG */
|
||||
__sbit __at (0x99) TI ; /* TRANSMIT Interrupt FLAG */
|
||||
__sbit __at (0x9A) RB8 ; /* RECEIVE BIT 8 */
|
||||
__sbit __at (0x9B) TB8 ; /* TRANSMIT BIT 8 */
|
||||
__sbit __at (0x9C) REN ; /* RECEIVE Enable */
|
||||
__sbit __at (0x9D) SM2 ; /* MULTIPROCESSOR COMMUNICATION Enable */
|
||||
__sbit __at (0x9E) SM1 ; /* SERIAL MODE Control BIT 1 */
|
||||
__sbit __at (0x9F) SM0 ; /* SERIAL MODE Control BIT 0 */
|
||||
|
||||
/* P2 0xA0 */
|
||||
__sbit __at (0xA0) P2_0 ;
|
||||
__sbit __at (0xA1) P2_1 ;
|
||||
__sbit __at (0xA2) P2_2 ;
|
||||
__sbit __at (0xA3) P2_3 ;
|
||||
__sbit __at (0xA4) P2_4 ; /* Port2 I/O Bits */
|
||||
__sbit __at (0xA5) P2_5 ;
|
||||
__sbit __at (0xA6) P2_6 ;
|
||||
__sbit __at (0xA7) P2_7 ;
|
||||
|
||||
/* IE 0xA8 */
|
||||
__sbit __at (0xA8) EX0 ; /* EXTERNAL Interrupt 0 Enable */
|
||||
__sbit __at (0xA9) ET0 ; /* TIMER 0 Interrupt Enable */
|
||||
__sbit __at (0xAA) EX1 ; /* EXTERNAL Interrupt 1 Enable */
|
||||
__sbit __at (0xAB) ET1 ; /* TIMER 1 Interrupt Enable */
|
||||
__sbit __at (0xAC) ES ; /* SERIAL PORT Interrupt Enable */
|
||||
__sbit __at (0xAD) ET2 ; /* TIMER 2 Interrupt Enable */
|
||||
//------------- /* Bit 6 not used */
|
||||
__sbit __at (0xAF) EA ; /* GLOBAL Interrupt Enable */
|
||||
|
||||
/* P2 0xB0 */
|
||||
__sbit __at (0xB0) P3_0 ;
|
||||
__sbit __at (0xB1) P3_1 ;
|
||||
__sbit __at (0xB2) P3_2 ;
|
||||
__sbit __at (0xB3) P3_3 ;
|
||||
__sbit __at (0xB4) P3_4 ; /* Port3 I/O Bits */
|
||||
__sbit __at (0xB5) P3_5 ;
|
||||
__sbit __at (0xB6) P3_6 ;
|
||||
__sbit __at (0xB7) P3_7 ;
|
||||
|
||||
/* IP 0xB8 */
|
||||
__sbit __at (0xB8) PX0 ; /* EXTERNAL Interrupt 0 Priority */
|
||||
__sbit __at (0xB9) PT0 ; /* TIMER 0 Priority */
|
||||
__sbit __at (0xBA) PX1 ; /* EXTERNAL Interrupt 1 Priority */
|
||||
__sbit __at (0xBB) PT1 ; /* TIMER 1 Priority */
|
||||
__sbit __at (0xBC) PS ; /* SERIAL PORT Priority */
|
||||
__sbit __at (0xBD) PT2 ; /* TIMER 2 Priority */
|
||||
//------------- /* Bit 6 not used */
|
||||
//------------- /* Bit 7 not used */
|
||||
|
||||
/* T2CON 0xC8 */
|
||||
__sbit __at (0xC8) CPRL2 ; /* CAPTURE OR RELOAD SELECT */
|
||||
__sbit __at (0xC9) CT2 ; /* TIMER OR COUNTER SELECT */
|
||||
__sbit __at (0xCA) TR2 ; /* TIMER 2 ON/OFF Control */
|
||||
__sbit __at (0xCB) EXEN2 ; /* TIMER 2 EXTERNAL Enable FLAG */
|
||||
__sbit __at (0xCC) TCLK ; /* TRANSMIT CLOCK FLAG */
|
||||
__sbit __at (0xCD) RCLK ; /* RECEIVE CLOCK FLAG */
|
||||
__sbit __at (0xCE) EXF2 ; /* EXTERNAL FLAG */
|
||||
__sbit __at (0xCF) TF2 ; /* TIMER 2 Overflow FLAG */
|
||||
|
||||
/* PSW 0xD0 */
|
||||
__sbit __at (0xD0) P ; /* ACCUMULATOR PARITY FLAG */
|
||||
__sbit __at (0xD1) F1 ; /* USER FLAG 1 */
|
||||
__sbit __at (0xD2) OV ; /* Overflow FLAG */
|
||||
__sbit __at (0xD3) RS0 ; /* Register BANK SELECT 0 */
|
||||
__sbit __at (0xD4) RS1 ; /* Register BANK SELECT 1 */
|
||||
__sbit __at (0xD5) F0 ; /* USER FLAG 0 */
|
||||
__sbit __at (0xD6) AC ; /* AUXILIARY CARRY FLAG */
|
||||
__sbit __at (0xD7) CY ; /* CARRY FLAG */
|
||||
|
||||
/* ADC0CN 0xE8 */
|
||||
__sbit __at (0xE8) ADLJST ; /* Left Justify Data (F206 only) */
|
||||
__sbit __at (0xE9) ADWINT ; /* WINDOW COMPARE Interrupt FLAG */
|
||||
__sbit __at (0xEA) ADSTM0 ; /* START OF CONVERSION MODE BIT 0 */
|
||||
__sbit __at (0xEB) ADSTM1 ; /* START OF CONVERSION MODE BIT 1 */
|
||||
__sbit __at (0xEC) ADBUSY ; /* BUSY FLAG */
|
||||
__sbit __at (0xED) ADCINT ; /* CONVERISION COMPLETE Interrupt FLAG */
|
||||
__sbit __at (0xEE) ADCTM ; /* TRACK MODE */
|
||||
__sbit __at (0xEF) ADCEN ; /* Enable */
|
||||
|
||||
/* SPI0CN 0xF8 */
|
||||
__sbit __at (0xF8) SPIEN ; /* SPI Enable */
|
||||
__sbit __at (0xF9) MSTEN ; /* MASTER Enable */
|
||||
__sbit __at (0xFA) SLVSEL ; /* SLAVE SELECT */
|
||||
__sbit __at (0xFB) TXBSY ; /* TX BUSY FLAG */
|
||||
__sbit __at (0xFC) RXOVRN ; /* RX OVERRUN FLAG */
|
||||
__sbit __at (0xFD) MODF ; /* MODE FAULT FLAG */
|
||||
__sbit __at (0xFE) WCOL ; /* WRITE COLLISION FLAG */
|
||||
__sbit __at (0xFF) SPIF ; /* Interrupt FLAG */
|
||||
|
||||
#endif
|
||||
268
lib/mcs51/C8051F300.h
Normal file
268
lib/mcs51/C8051F300.h
Normal file
@@ -0,0 +1,268 @@
|
||||
/*-------------------------------------------------------------------------
|
||||
C8051F300.h - Register Declarations for the Cygnal/SiLabs C8051F30x
|
||||
Processor Range
|
||||
|
||||
Copyright (C) 2004, Maarten Brock, sourceforge.brock@dse.nl
|
||||
|
||||
This library is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the
|
||||
Free Software Foundation; either version 2, or (at your option) any
|
||||
later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this library; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
|
||||
MA 02110-1301, USA.
|
||||
|
||||
As a special exception, if you link this library with other files,
|
||||
some of which are compiled with SDCC, to produce an executable,
|
||||
this library does not by itself cause the resulting executable to
|
||||
be covered by the GNU General Public License. This exception does
|
||||
not however invalidate any other reasons why the executable file
|
||||
might be covered by the GNU General Public License.
|
||||
-------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef C8051F300_H
|
||||
#define C8051F300_H
|
||||
|
||||
|
||||
/* BYTE Registers */
|
||||
|
||||
__sfr __at (0x80) P0 ; /* PORT 0 */
|
||||
__sfr __at (0x81) SP ; /* STACK POINTER */
|
||||
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
|
||||
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
|
||||
__sfr __at (0x87) PCON ; /* POWER CONTROL */
|
||||
__sfr __at (0x88) TCON ; /* TIMER CONTROL */
|
||||
__sfr __at (0x89) TMOD ; /* TIMER MODE */
|
||||
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
|
||||
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
|
||||
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
|
||||
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
|
||||
__sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
|
||||
__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
|
||||
__sfr __at (0x98) SCON ; /* SERIAL PORT CONTROL */
|
||||
__sfr __at (0x98) SCON0 ; /* SERIAL PORT CONTROL */
|
||||
__sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
|
||||
__sfr __at (0x99) SBUF0 ; /* SERIAL PORT BUFFER */
|
||||
__sfr __at (0x9D) CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
|
||||
__sfr __at (0x9F) CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
|
||||
__sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
|
||||
__sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at (0xB3) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
|
||||
__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
|
||||
__sfr __at (0xB7) FLKEY ; /* FLASH ACESS LIMIT */
|
||||
__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
|
||||
__sfr __at (0xBB) AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
|
||||
__sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */
|
||||
__sfr __at (0xBE) ADC0 ; /* ADC 0 DATA */
|
||||
__sfr __at (0xC0) SMB0CN ; /* SMBUS CONTROL */
|
||||
__sfr __at (0xC1) SMB0CF ; /* SMBUS CONFIGURATION */
|
||||
__sfr __at (0xC2) SMB0DAT ; /* SMBUS DATA */
|
||||
__sfr __at (0xC4) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER */
|
||||
__sfr __at (0xC6) ADC0LT ; /* ADC 0 LESS-THAN REGISTER */
|
||||
__sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
|
||||
__sfr __at (0xC8) TMR2CN ; /* TIMER 2 CONTROL */
|
||||
__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at (0xCA) TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xCB) TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
|
||||
__sfr __at (0xCC) TMR2L ; /* TIMER 2 - LOW BYTE */
|
||||
__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
|
||||
__sfr __at (0xCD) TMR2H ; /* TIMER 2 - HIGH BYTE */
|
||||
__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
|
||||
__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
|
||||
__sfr __at (0xD8) PCA0CN ; /* PCA CONTROL */
|
||||
__sfr __at (0xD9) PCA0MD ; /* PCA MODE */
|
||||
__sfr __at (0xDA) PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
|
||||
__sfr __at (0xDB) PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
|
||||
__sfr __at (0xDC) PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
|
||||
__sfr __at (0xE0) ACC ; /* ACCUMULATOR */
|
||||
__sfr __at (0xE1) PRT0MX ; /* PORT MUX CONFIGURATION REGISTER 0 */
|
||||
__sfr __at (0xE1) XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
|
||||
__sfr __at (0xE2) PRT1MX ; /* PORT MUX CONFIGURATION REGISTER 1 */
|
||||
__sfr __at (0xE2) XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
|
||||
__sfr __at (0xE3) PRT2MX ; /* PORT MUX CONFIGURATION REGISTER 2 */
|
||||
__sfr __at (0xE3) XBR2 ; /* PORT MUX CONFIGURATION REGISTER 2 */
|
||||
__sfr __at (0xE4) IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
|
||||
__sfr __at (0xE4) INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
|
||||
__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
|
||||
__sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */
|
||||
__sfr __at (0xE9) PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
|
||||
__sfr __at (0xEA) PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
|
||||
__sfr __at (0xEB) PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
|
||||
__sfr __at (0xEC) PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
|
||||
__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
|
||||
__sfr __at (0xF0) B ; /* B REGISTER */
|
||||
__sfr __at (0xF1) P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF1) P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
|
||||
__sfr __at (0xF8) CPT0CN ; /* COMPARATOR 0 CONTROL */
|
||||
__sfr __at (0xF9) PCA0L ; /* PCA COUNTER LOW */
|
||||
__sfr __at (0xFA) PCA0H ; /* PCA COUNTER HIGH */
|
||||
__sfr __at (0xFB) PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
|
||||
__sfr __at (0xFC) PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
|
||||
|
||||
|
||||
/* WORD/DWORD Registers */
|
||||
|
||||
__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
|
||||
__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
|
||||
__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
|
||||
__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
|
||||
__sfr16 __at (0xCBCA) TMR2RL ; /* TIMER 2 CAPTURE REGISTER WORD */
|
||||
__sfr16 __at (0xFAF9) PCA0 ; /* PCA COUNTER */
|
||||
__sfr16 __at (0xFCFB) PCA0CP0 ; /* PCA CAPTURE 0 WORD */
|
||||
__sfr16 __at (0xEAE9) PCA0CP1 ; /* PCA CAPTURE 1 WORD */
|
||||
__sfr16 __at (0xECEB) PCA0CP2 ; /* PCA CAPTURE 2 WORD */
|
||||
|
||||
|
||||
/* BIT Registers */
|
||||
|
||||
/* P0 0x80 */
|
||||
__sbit __at (0x80) P0_0 ;
|
||||
__sbit __at (0x81) P0_1 ;
|
||||
__sbit __at (0x82) P0_2 ;
|
||||
__sbit __at (0x83) P0_3 ;
|
||||
__sbit __at (0x84) P0_4 ;
|
||||
__sbit __at (0x85) P0_5 ;
|
||||
__sbit __at (0x86) P0_6 ;
|
||||
__sbit __at (0x87) P0_7 ;
|
||||
|
||||
/* TCON 0x88 */
|
||||
__sbit __at (0x88) IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
|
||||
__sbit __at (0x89) IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
|
||||
__sbit __at (0x8A) IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
|
||||
__sbit __at (0x8B) IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
|
||||
__sbit __at (0x8C) TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
|
||||
__sbit __at (0x8D) TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
|
||||
__sbit __at (0x8E) TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
|
||||
__sbit __at (0x8F) TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
|
||||
|
||||
/* SCON 0x98 */
|
||||
__sbit __at (0x98) RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
|
||||
__sbit __at (0x98) RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
|
||||
__sbit __at (0x99) TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
|
||||
__sbit __at (0x99) TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
|
||||
__sbit __at (0x9A) RB8 ; /* SCON.2 - RECEIVE BIT 8 */
|
||||
__sbit __at (0x9A) RB80 ; /* SCON.2 - RECEIVE BIT 8 */
|
||||
__sbit __at (0x9B) TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
|
||||
__sbit __at (0x9B) TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
|
||||
__sbit __at (0x9C) REN ; /* SCON.4 - RECEIVE ENABLE */
|
||||
__sbit __at (0x9C) REN0 ; /* SCON.4 - RECEIVE ENABLE */
|
||||
__sbit __at (0x9D) SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
|
||||
__sbit __at (0x9D) MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
|
||||
__sbit __at (0x9F) SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
|
||||
__sbit __at (0x9F) S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
|
||||
|
||||
/* IE 0xA8 */
|
||||
__sbit __at (0xA8) EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
|
||||
__sbit __at (0xA9) ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAA) EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
|
||||
__sbit __at (0xAB) ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAC) ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
|
||||
__sbit __at (0xAC) ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
|
||||
__sbit __at (0xAD) ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAE) IEGF0 ; /* IE.6 - GENERAL PURPOSE FLAG 0 */
|
||||
__sbit __at (0xAF) EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
|
||||
|
||||
/* IP 0xB8 */
|
||||
__sbit __at (0xB8) PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
|
||||
__sbit __at (0xB9) PT0 ; /* IP.1 - TIMER 0 PRIORITY */
|
||||
__sbit __at (0xBA) PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
|
||||
__sbit __at (0xBB) PT1 ; /* IP.3 - TIMER 1 PRIORITY */
|
||||
__sbit __at (0xBC) PS ; /* IP.4 - SERIAL PORT PRIORITY */
|
||||
__sbit __at (0xBC) PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
|
||||
__sbit __at (0xBD) PT2 ; /* IP.5 - TIMER 2 PRIORITY */
|
||||
|
||||
/* SMB0CN 0xC0 */
|
||||
__sbit __at (0xC0) SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
|
||||
__sbit __at (0xC1) ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
|
||||
__sbit __at (0xC2) ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
|
||||
__sbit __at (0xC3) ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
|
||||
__sbit __at (0xC4) STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
|
||||
__sbit __at (0xC5) STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
|
||||
__sbit __at (0xC6) TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
|
||||
__sbit __at (0xC7) MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
|
||||
|
||||
/* TMR2CN 0xC8 */
|
||||
__sbit __at (0xC8) T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
|
||||
__sbit __at (0xCA) TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
|
||||
__sbit __at (0xCB) T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
|
||||
__sbit __at (0xCD) TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
|
||||
__sbit __at (0xCE) TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
|
||||
__sbit __at (0xCF) TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
|
||||
__sbit __at (0xCF) TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
|
||||
|
||||
/* PSW 0xD0 */
|
||||
__sbit __at (0xD0) PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
|
||||
__sbit __at (0xD1) F1 ; /* PSW.1 - FLAG 1 */
|
||||
__sbit __at (0xD2) OV ; /* PSW.2 - OVERFLOW FLAG */
|
||||
__sbit __at (0xD3) RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
|
||||
__sbit __at (0xD4) RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
|
||||
__sbit __at (0xD5) F0 ; /* PSW.5 - FLAG 0 */
|
||||
__sbit __at (0xD6) AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
|
||||
__sbit __at (0xD7) CY ; /* PSW.7 - CARRY FLAG */
|
||||
|
||||
/* PCA0CN 0xD8 */
|
||||
__sbit __at (0xD8) CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
|
||||
__sbit __at (0xD9) CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
|
||||
__sbit __at (0xDA) CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
|
||||
__sbit __at (0xDE) CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
|
||||
__sbit __at (0xDF) CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
|
||||
|
||||
/* ADC0CN 0xE8 */
|
||||
__sbit __at (0xE8) AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
|
||||
__sbit __at (0xE9) AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
|
||||
__sbit __at (0xEA) AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
|
||||
__sbit __at (0xEB) AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
|
||||
__sbit __at (0xEC) AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
|
||||
__sbit __at (0xED) AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
|
||||
__sbit __at (0xEE) AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */
|
||||
__sbit __at (0xEF) AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */
|
||||
|
||||
/* CPT0CN 0xF8 */
|
||||
__sbit __at (0xF8) CP0HYN0 ; /* CPT0CN.0 - Comp.0 Neg. Hysteresis Control Bit0*/
|
||||
__sbit __at (0xF9) CP0HYN1 ; /* CPT0CN.1 - Comp.0 Neg. Hysteresis Control Bit1*/
|
||||
__sbit __at (0xFA) CP0HYP0 ; /* CPT0CN.2 - Comp.0 Pos. Hysteresis Control Bit0*/
|
||||
__sbit __at (0xFB) CP0HYP1 ; /* CPT0CN.3 - Comp.0 Pos. Hysteresis Control Bit1*/
|
||||
__sbit __at (0xFC) CP0FIF ; /* CPT0CN.4 - Comparator0 Falling-Edge Int. Flag */
|
||||
__sbit __at (0xFD) CP0RIF ; /* CPT0CN.5 - Comparator0 Rising-Edge Int. Flag */
|
||||
__sbit __at (0xFE) CP0OUT ; /* CPT0CN.6 - Comparator0 Output State Flag */
|
||||
__sbit __at (0xFF) CP0EN ; /* CPT0CN.7 - Comparator0 Enable Bit */
|
||||
|
||||
|
||||
/* Predefined SFR Bit Masks */
|
||||
|
||||
#define PCON_IDLE 0x01 /* PCON */
|
||||
#define PCON_STOP 0x02 /* PCON */
|
||||
#define T1M 0x10 /* CKCON */
|
||||
#define PSWE 0x01 /* PSCTL */
|
||||
#define PSEE 0x02 /* PSCTL */
|
||||
#define ECP0F 0x10 /* EIE1 */
|
||||
#define ECP0R 0x20 /* EIE1 */
|
||||
#define PORSF 0x02 /* RSTSRC */
|
||||
#define SWRSF 0x10 /* RSTSRC */
|
||||
#define ECCF 0x01 /* PCA0CPMn */
|
||||
#define PWM 0x02 /* PCA0CPMn */
|
||||
#define TOG 0x04 /* PCA0CPMn */
|
||||
#define MAT 0x08 /* PCA0CPMn */
|
||||
#define CAPN 0x10 /* PCA0CPMn */
|
||||
#define CAPP 0x20 /* PCA0CPMn */
|
||||
#define ECOM 0x40 /* PCA0CPMn */
|
||||
#define PWM16 0x80 /* PCA0CPMn */
|
||||
#define CP0E 0x10 /* XBR1 */
|
||||
#define CP0OEN 0x10 /* XBR1 */
|
||||
#define CP0AE 0x20 /* XBR1 */
|
||||
#define CP0AOEN 0x20 /* XBR1 */
|
||||
|
||||
#endif
|
||||
346
lib/mcs51/C8051F310.h
Normal file
346
lib/mcs51/C8051F310.h
Normal file
@@ -0,0 +1,346 @@
|
||||
/*-------------------------------------------------------------------------
|
||||
C8051F310.h - Register Declarations for the Cygnal/SiLabs C8051F31x
|
||||
Processor Range
|
||||
|
||||
Copyright (C) 2004, Maarten Brock, sourceforge.brock@dse.nl
|
||||
|
||||
This library is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the
|
||||
Free Software Foundation; either version 2, or (at your option) any
|
||||
later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this library; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
|
||||
MA 02110-1301, USA.
|
||||
|
||||
As a special exception, if you link this library with other files,
|
||||
some of which are compiled with SDCC, to produce an executable,
|
||||
this library does not by itself cause the resulting executable to
|
||||
be covered by the GNU General Public License. This exception does
|
||||
not however invalidate any other reasons why the executable file
|
||||
might be covered by the GNU General Public License.
|
||||
-------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef C8051F310_H
|
||||
#define C8051F310_H
|
||||
|
||||
|
||||
/* BYTE Registers */
|
||||
|
||||
__sfr __at (0x80) P0 ; /* PORT 0 */
|
||||
__sfr __at (0x81) SP ; /* STACK POINTER */
|
||||
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
|
||||
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
|
||||
__sfr __at (0x87) PCON ; /* POWER CONTROL */
|
||||
__sfr __at (0x88) TCON ; /* TIMER CONTROL */
|
||||
__sfr __at (0x89) TMOD ; /* TIMER MODE */
|
||||
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
|
||||
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
|
||||
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
|
||||
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
|
||||
__sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
|
||||
__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
|
||||
__sfr __at (0x90) P1 ; /* PORT 1 */
|
||||
__sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */
|
||||
__sfr __at (0x92) TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at (0x93) TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */
|
||||
__sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */
|
||||
__sfr __at (0x98) SCON ; /* SERIAL PORT CONTROL */
|
||||
__sfr __at (0x98) SCON0 ; /* SERIAL PORT CONTROL */
|
||||
__sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
|
||||
__sfr __at (0x99) SBUF0 ; /* SERIAL PORT BUFFER */
|
||||
__sfr __at (0x9A) CPT1CN ; /* COMPARATOR 1 CONTROL */
|
||||
__sfr __at (0x9B) CPT0CN ; /* COMPARATOR 0 CONTROL */
|
||||
__sfr __at (0x9C) CPT1MD ; /* COMPARATOR 1 MODE SELECTION */
|
||||
__sfr __at (0x9D) CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
|
||||
__sfr __at (0x9E) CPT1MX ; /* COMPARATOR 1 MUX SELECTION */
|
||||
__sfr __at (0x9F) CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
|
||||
__sfr __at (0xA0) P2 ; /* PORT 2 */
|
||||
__sfr __at (0xA1) SPI0CFG ; /* SPI0 CONFIGURATION */
|
||||
__sfr __at (0xA2) SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */
|
||||
__sfr __at (0xA3) SPI0DAT ; /* SPI0 DATA */
|
||||
__sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA5) P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA7) P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
|
||||
__sfr __at (0xA9) CLKSEL ; /* SYSTEM CLOCK SELECT */
|
||||
__sfr __at (0xAA) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
|
||||
__sfr __at (0xAA) _XPAGE ; /* XDATA/PDATA PAGE */
|
||||
__sfr __at (0xB0) P3 ; /* PORT 3 */
|
||||
__sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at (0xB3) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
|
||||
__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
|
||||
__sfr __at (0xB7) FLKEY ; /* FLASH ACESS LIMIT */
|
||||
__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
|
||||
__sfr __at (0xBA) AMX0N ; /* ADC 0 MUX NEGATIVE CHANNEL SELECTION */
|
||||
__sfr __at (0xBB) AMX0P ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */
|
||||
__sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */
|
||||
__sfr __at (0xBD) ADC0L ; /* ADC 0 DATA WORD LSB */
|
||||
__sfr __at (0xBE) ADC0H ; /* ADC 0 DATA WORD MSB */
|
||||
__sfr __at (0xC0) SMB0CN ; /* SMBUS CONTROL */
|
||||
__sfr __at (0xC1) SMB0CF ; /* SMBUS CONFIGURATION */
|
||||
__sfr __at (0xC2) SMB0DAT ; /* SMBUS DATA */
|
||||
__sfr __at (0xC3) ADC0GTL ; /* ADC 0 GREATER-THAN LOW BYTE */
|
||||
__sfr __at (0xC4) ADC0GTH ; /* ADC 0 GREATER-THAN HIGH BYTE */
|
||||
__sfr __at (0xC5) ADC0LTL ; /* ADC 0 LESS-THAN LOW BYTE */
|
||||
__sfr __at (0xC6) ADC0LTH ; /* ADC 0 LESS-THAN HIGH BYTE */
|
||||
__sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
|
||||
__sfr __at (0xC8) TMR2CN ; /* TIMER 2 CONTROL */
|
||||
__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at (0xCA) TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xCB) TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
|
||||
__sfr __at (0xCC) TMR2L ; /* TIMER 2 - LOW BYTE */
|
||||
__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
|
||||
__sfr __at (0xCD) TMR2H ; /* TIMER 2 - HIGH BYTE */
|
||||
__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
|
||||
__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
|
||||
__sfr __at (0xD4) P0SKIP ; /* PORT 0 SKIP */
|
||||
__sfr __at (0xD5) P1SKIP ; /* PORT 1 SKIP */
|
||||
__sfr __at (0xD6) P2SKIP ; /* PORT 2 SKIP */
|
||||
__sfr __at (0xD8) PCA0CN ; /* PCA CONTROL */
|
||||
__sfr __at (0xD9) PCA0MD ; /* PCA MODE */
|
||||
__sfr __at (0xDA) PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
|
||||
__sfr __at (0xDB) PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
|
||||
__sfr __at (0xDC) PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
|
||||
__sfr __at (0xDD) PCA0CPM3 ; /* PCA MODULE 3 MODE REGISTER */
|
||||
__sfr __at (0xDE) PCA0CPM4 ; /* PCA MODULE 4 MODE REGISTER */
|
||||
__sfr __at (0xE0) ACC ; /* ACCUMULATOR */
|
||||
__sfr __at (0xE1) XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
|
||||
__sfr __at (0xE2) XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
|
||||
__sfr __at (0xE4) IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
|
||||
__sfr __at (0xE4) INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
|
||||
__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
|
||||
__sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */
|
||||
__sfr __at (0xE9) PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
|
||||
__sfr __at (0xEA) PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
|
||||
__sfr __at (0xEB) PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
|
||||
__sfr __at (0xEC) PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
|
||||
__sfr __at (0xED) PCA0CPL3 ; /* PCA CAPTURE 3 LOW */
|
||||
__sfr __at (0xEE) PCA0CPH3 ; /* PCA CAPTURE 3 HIGH */
|
||||
__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
|
||||
__sfr __at (0xF0) B ; /* B REGISTER */
|
||||
__sfr __at (0xF1) P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF1) P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF2) P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF2) P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF3) P2MODE ; /* PORT 2 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF3) P2MDIN ; /* PORT 2 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF4) P3MODE ; /* PORT 3 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF4) P3MDIN ; /* PORT 3 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
|
||||
__sfr __at (0xF8) SPI0CN ; /* SPI0 CONTROL */
|
||||
__sfr __at (0xF9) PCA0L ; /* PCA COUNTER LOW */
|
||||
__sfr __at (0xFA) PCA0H ; /* PCA COUNTER HIGH */
|
||||
__sfr __at (0xFB) PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
|
||||
__sfr __at (0xFC) PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
|
||||
__sfr __at (0xFD) PCA0CPL4 ; /* PCA CAPTURE 4 LOW */
|
||||
__sfr __at (0xFE) PCA0CPH4 ; /* PCA CAPTURE 4 HIGH */
|
||||
__sfr __at (0xFF) VDM0CN ; /* VDD MONITOR CONTROL */
|
||||
|
||||
|
||||
/* WORD/DWORD Registers */
|
||||
|
||||
__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
|
||||
__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
|
||||
__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
|
||||
__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
|
||||
__sfr16 __at (0xCBCA) TMR2RL ; /* TIMER 2 CAPTURE REGISTER WORD */
|
||||
__sfr16 __at (0x9594) TMR3 ; /* TIMER 3 COUNTER */
|
||||
__sfr16 __at (0x9392) TMR3RL ; /* TIMER 3 CAPTURE REGISTER WORD */
|
||||
__sfr16 __at (0xBEBD) ADC0 ; /* ADC 0 DATA WORD */
|
||||
__sfr16 __at (0xC4C3) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */
|
||||
__sfr16 __at (0xC6C5) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */
|
||||
__sfr16 __at (0xFAF9) PCA0 ; /* PCA COUNTER */
|
||||
__sfr16 __at (0xFCFB) PCA0CP0 ; /* PCA CAPTURE 0 WORD */
|
||||
__sfr16 __at (0xEAE9) PCA0CP1 ; /* PCA CAPTURE 1 WORD */
|
||||
__sfr16 __at (0xECEB) PCA0CP2 ; /* PCA CAPTURE 2 WORD */
|
||||
__sfr16 __at (0xEEED) PCA0CP3 ; /* PCA CAPTURE 3 WORD */
|
||||
__sfr16 __at (0xFEFD) PCA0CP4 ; /* PCA CAPTURE 4 WORD */
|
||||
|
||||
|
||||
/* BIT Registers */
|
||||
|
||||
/* P0 0x80 */
|
||||
__sbit __at (0x80) P0_0 ;
|
||||
__sbit __at (0x81) P0_1 ;
|
||||
__sbit __at (0x82) P0_2 ;
|
||||
__sbit __at (0x83) P0_3 ;
|
||||
__sbit __at (0x84) P0_4 ;
|
||||
__sbit __at (0x85) P0_5 ;
|
||||
__sbit __at (0x86) P0_6 ;
|
||||
__sbit __at (0x87) P0_7 ;
|
||||
|
||||
/* TCON 0x88 */
|
||||
__sbit __at (0x88) IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
|
||||
__sbit __at (0x89) IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
|
||||
__sbit __at (0x8A) IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
|
||||
__sbit __at (0x8B) IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
|
||||
__sbit __at (0x8C) TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
|
||||
__sbit __at (0x8D) TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
|
||||
__sbit __at (0x8E) TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
|
||||
__sbit __at (0x8F) TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
|
||||
|
||||
/* P1 0x90 */
|
||||
__sbit __at (0x90) P1_0 ;
|
||||
__sbit __at (0x91) P1_1 ;
|
||||
__sbit __at (0x92) P1_2 ;
|
||||
__sbit __at (0x93) P1_3 ;
|
||||
__sbit __at (0x94) P1_4 ;
|
||||
__sbit __at (0x95) P1_5 ;
|
||||
__sbit __at (0x96) P1_6 ;
|
||||
__sbit __at (0x97) P1_7 ;
|
||||
|
||||
/* SCON 0x98 */
|
||||
__sbit __at (0x98) RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
|
||||
__sbit __at (0x98) RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
|
||||
__sbit __at (0x99) TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
|
||||
__sbit __at (0x99) TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
|
||||
__sbit __at (0x9A) RB8 ; /* SCON.2 - RECEIVE BIT 8 */
|
||||
__sbit __at (0x9A) RB80 ; /* SCON.2 - RECEIVE BIT 8 */
|
||||
__sbit __at (0x9B) TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
|
||||
__sbit __at (0x9B) TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
|
||||
__sbit __at (0x9C) REN ; /* SCON.4 - RECEIVE ENABLE */
|
||||
__sbit __at (0x9C) REN0 ; /* SCON.4 - RECEIVE ENABLE */
|
||||
__sbit __at (0x9D) SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
|
||||
__sbit __at (0x9D) MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
|
||||
__sbit __at (0x9F) SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
|
||||
__sbit __at (0x9F) S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
|
||||
|
||||
/* P2 0xA0 */
|
||||
__sbit __at (0xA0) P2_0 ;
|
||||
__sbit __at (0xA1) P2_1 ;
|
||||
__sbit __at (0xA2) P2_2 ;
|
||||
__sbit __at (0xA3) P2_3 ;
|
||||
__sbit __at (0xA4) P2_4 ;
|
||||
__sbit __at (0xA5) P2_5 ;
|
||||
__sbit __at (0xA6) P2_6 ;
|
||||
__sbit __at (0xA7) P2_7 ;
|
||||
|
||||
/* IE 0xA8 */
|
||||
__sbit __at (0xA8) EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
|
||||
__sbit __at (0xA9) ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAA) EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
|
||||
__sbit __at (0xAB) ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAC) ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
|
||||
__sbit __at (0xAC) ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
|
||||
__sbit __at (0xAD) ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAE) ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAF) EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
|
||||
|
||||
/* P3 0xB0 */
|
||||
__sbit __at (0xB0) P3_0 ;
|
||||
__sbit __at (0xB1) P3_1 ;
|
||||
__sbit __at (0xB2) P3_2 ;
|
||||
__sbit __at (0xB3) P3_3 ;
|
||||
__sbit __at (0xB4) P3_4 ;
|
||||
__sbit __at (0xB5) P3_5 ;
|
||||
__sbit __at (0xB6) P3_6 ;
|
||||
__sbit __at (0xB7) P3_7 ;
|
||||
|
||||
/* IP 0xB8 */
|
||||
__sbit __at (0xB8) PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
|
||||
__sbit __at (0xB9) PT0 ; /* IP.1 - TIMER 0 PRIORITY */
|
||||
__sbit __at (0xBA) PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
|
||||
__sbit __at (0xBB) PT1 ; /* IP.3 - TIMER 1 PRIORITY */
|
||||
__sbit __at (0xBC) PS ; /* IP.4 - SERIAL PORT PRIORITY */
|
||||
__sbit __at (0xBC) PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
|
||||
__sbit __at (0xBD) PT2 ; /* IP.5 - TIMER 2 PRIORITY */
|
||||
__sbit __at (0xBE) PSPI0 ; /* IP.6 - SPI0 PRIORITY */
|
||||
|
||||
/* SMB0CN 0xC0 */
|
||||
__sbit __at (0xC0) SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
|
||||
__sbit __at (0xC1) ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
|
||||
__sbit __at (0xC2) ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
|
||||
__sbit __at (0xC3) ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
|
||||
__sbit __at (0xC4) STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
|
||||
__sbit __at (0xC5) STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
|
||||
__sbit __at (0xC6) TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
|
||||
__sbit __at (0xC7) MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
|
||||
|
||||
/* TMR2CN 0xC8 */
|
||||
__sbit __at (0xC8) T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
|
||||
__sbit __at (0xCA) TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
|
||||
__sbit __at (0xCB) T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
|
||||
__sbit __at (0xCD) TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
|
||||
__sbit __at (0xCE) TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
|
||||
__sbit __at (0xCF) TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
|
||||
__sbit __at (0xCF) TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
|
||||
|
||||
/* PSW 0xD0 */
|
||||
__sbit __at (0xD0) PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
|
||||
__sbit __at (0xD1) F1 ; /* PSW.1 - FLAG 1 */
|
||||
__sbit __at (0xD2) OV ; /* PSW.2 - OVERFLOW FLAG */
|
||||
__sbit __at (0xD3) RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
|
||||
__sbit __at (0xD4) RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
|
||||
__sbit __at (0xD5) F0 ; /* PSW.5 - FLAG 0 */
|
||||
__sbit __at (0xD6) AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
|
||||
__sbit __at (0xD7) CY ; /* PSW.7 - CARRY FLAG */
|
||||
|
||||
/* PCA0CN 0xD8 */
|
||||
__sbit __at (0xD8) CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
|
||||
__sbit __at (0xD9) CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
|
||||
__sbit __at (0xDA) CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
|
||||
__sbit __at (0xDB) CCF3 ; /* PCA0CN.3 - PCA MODULE 3 CAPTURE/COMPARE FLAG */
|
||||
__sbit __at (0xDC) CCF4 ; /* PCA0CN.4 - PCA MODULE 4 CAPTURE/COMPARE FLAG */
|
||||
__sbit __at (0xDE) CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
|
||||
__sbit __at (0xDF) CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
|
||||
|
||||
/* ADC0CN 0xE8 */
|
||||
__sbit __at (0xE8) AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
|
||||
__sbit __at (0xE9) AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
|
||||
__sbit __at (0xEA) AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
|
||||
__sbit __at (0xEB) AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
|
||||
__sbit __at (0xEC) AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
|
||||
__sbit __at (0xED) AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
|
||||
__sbit __at (0xEE) AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */
|
||||
__sbit __at (0xEF) AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */
|
||||
|
||||
/* SPI0CN 0xF8 */
|
||||
__sbit __at (0xF8) SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */
|
||||
__sbit __at (0xF9) TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
|
||||
__sbit __at (0xFA) NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
|
||||
__sbit __at (0xFB) NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
|
||||
__sbit __at (0xFC) RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
|
||||
__sbit __at (0xFD) MODF ; /* SPI0CN.5 - MODE FAULT FLAG */
|
||||
__sbit __at (0xFE) WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */
|
||||
__sbit __at (0xFF) SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
|
||||
|
||||
|
||||
/* Predefined SFR Bit Masks */
|
||||
|
||||
#define PCON_IDLE 0x01 /* PCON */
|
||||
#define PCON_STOP 0x02 /* PCON */
|
||||
#define T1M 0x08 /* CKCON */
|
||||
#define PSWE 0x01 /* PSCTL */
|
||||
#define PSEE 0x02 /* PSCTL */
|
||||
#define ECP0 0x20 /* EIE1 */
|
||||
#define ECP1 0x40 /* EIE1 */
|
||||
#define PORSF 0x02 /* RSTSRC */
|
||||
#define SWRSF 0x10 /* RSTSRC */
|
||||
#define ECCF 0x01 /* PCA0CPMn */
|
||||
#define PWM 0x02 /* PCA0CPMn */
|
||||
#define TOG 0x04 /* PCA0CPMn */
|
||||
#define MAT 0x08 /* PCA0CPMn */
|
||||
#define CAPN 0x10 /* PCA0CPMn */
|
||||
#define CAPP 0x20 /* PCA0CPMn */
|
||||
#define ECOM 0x40 /* PCA0CPMn */
|
||||
#define PWM16 0x80 /* PCA0CPMn */
|
||||
#define CP0E 0x10 /* XBR0 */
|
||||
#define CP0OEN 0x10 /* XBR0 */
|
||||
#define CP0AE 0x20 /* XBR0 */
|
||||
#define CP0AOEN 0x20 /* XBR0 */
|
||||
#define CP1E 0x40 /* XBR0 */
|
||||
#define CP1AE 0x80 /* XBR0 */
|
||||
|
||||
#endif
|
||||
353
lib/mcs51/C8051F320.h
Normal file
353
lib/mcs51/C8051F320.h
Normal file
@@ -0,0 +1,353 @@
|
||||
/*-------------------------------------------------------------------------
|
||||
C8051F320.h - Register Declarations for the Cygnal/SiLabs C8051F32x
|
||||
Processor Range
|
||||
|
||||
Copyright (C) 2004, Maarten Brock, sourceforge.brock@dse.nl
|
||||
|
||||
This library is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the
|
||||
Free Software Foundation; either version 2, or (at your option) any
|
||||
later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this library; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
|
||||
MA 02110-1301, USA.
|
||||
|
||||
As a special exception, if you link this library with other files,
|
||||
some of which are compiled with SDCC, to produce an executable,
|
||||
this library does not by itself cause the resulting executable to
|
||||
be covered by the GNU General Public License. This exception does
|
||||
not however invalidate any other reasons why the executable file
|
||||
might be covered by the GNU General Public License.
|
||||
-------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef C8051F320_H
|
||||
#define C8051F320_H
|
||||
|
||||
|
||||
/* BYTE Registers */
|
||||
__sfr __at (0x80) P0 ; /* PORT 0 */
|
||||
__sfr __at (0x81) SP ; /* STACK POINTER */
|
||||
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
|
||||
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
|
||||
__sfr __at (0x87) PCON ; /* POWER CONTROL */
|
||||
__sfr __at (0x88) TCON ; /* TIMER CONTROL */
|
||||
__sfr __at (0x89) TMOD ; /* TIMER MODE */
|
||||
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
|
||||
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
|
||||
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
|
||||
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
|
||||
__sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
|
||||
__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
|
||||
__sfr __at (0x90) P1 ; /* PORT 1 */
|
||||
__sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */
|
||||
__sfr __at (0x92) TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at (0x93) TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */
|
||||
__sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */
|
||||
__sfr __at (0x96) USB0ADR ; /* USB0 INDIRECT ADDRESS REGISTER */
|
||||
__sfr __at (0x97) USB0DAT ; /* USB0 DATA REGISTER */
|
||||
__sfr __at (0x98) SCON ; /* SERIAL PORT CONTROL */
|
||||
__sfr __at (0x98) SCON0 ; /* SERIAL PORT CONTROL */
|
||||
__sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
|
||||
__sfr __at (0x99) SBUF0 ; /* SERIAL PORT BUFFER */
|
||||
__sfr __at (0x9A) CPT1CN ; /* COMPARATOR 1 CONTROL */
|
||||
__sfr __at (0x9B) CPT0CN ; /* COMPARATOR 0 CONTROL */
|
||||
__sfr __at (0x9C) CPT1MD ; /* COMPARATOR 1 MODE SELECTION */
|
||||
__sfr __at (0x9D) CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
|
||||
__sfr __at (0x9E) CPT1MX ; /* COMPARATOR 1 MUX SELECTION */
|
||||
__sfr __at (0x9F) CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
|
||||
__sfr __at (0xA0) P2 ; /* PORT 2 */
|
||||
__sfr __at (0xA1) SPI0CFG ; /* SPI0 CONFIGURATION */
|
||||
__sfr __at (0xA2) SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */
|
||||
__sfr __at (0xA3) SPI0DAT ; /* SPI0 DATA */
|
||||
__sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA5) P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA7) P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
|
||||
__sfr __at (0xA9) CLKSEL ; /* SYSTEM CLOCK SELECT */
|
||||
__sfr __at (0xAA) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
|
||||
__sfr __at (0xAA) _XPAGE ; /* XDATA/PDATA PAGE */
|
||||
__sfr __at (0xB0) P3 ; /* PORT 3 */
|
||||
__sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at (0xB3) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
|
||||
__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
|
||||
__sfr __at (0xB7) FLKEY ; /* FLASH ACESS LIMIT */
|
||||
__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
|
||||
__sfr __at (0xB9) CLKMUL ; /* CLOCK MULTIPLIER CONTROL REGISTER */
|
||||
__sfr __at (0xBA) AMX0N ; /* ADC 0 MUX NEGATIVE CHANNEL SELECTION */
|
||||
__sfr __at (0xBB) AMX0P ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */
|
||||
__sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */
|
||||
__sfr __at (0xBD) ADC0L ; /* ADC 0 DATA WORD LSB */
|
||||
__sfr __at (0xBE) ADC0H ; /* ADC 0 DATA WORD MSB */
|
||||
__sfr __at (0xC0) SMB0CN ; /* SMBUS CONTROL */
|
||||
__sfr __at (0xC1) SMB0CF ; /* SMBUS CONFIGURATION */
|
||||
__sfr __at (0xC2) SMB0DAT ; /* SMBUS DATA */
|
||||
__sfr __at (0xC3) ADC0GTL ; /* ADC 0 GREATER-THAN LOW BYTE */
|
||||
__sfr __at (0xC4) ADC0GTH ; /* ADC 0 GREATER-THAN HIGH BYTE */
|
||||
__sfr __at (0xC5) ADC0LTL ; /* ADC 0 LESS-THAN LOW BYTE */
|
||||
__sfr __at (0xC6) ADC0LTH ; /* ADC 0 LESS-THAN HIGH BYTE */
|
||||
__sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
|
||||
__sfr __at (0xC8) TMR2CN ; /* TIMER 2 CONTROL */
|
||||
__sfr __at (0xC9) REG0CN ; /* VOLTAGE REGULATOR CONTROL */
|
||||
__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at (0xCA) TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xCB) TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
|
||||
__sfr __at (0xCC) TMR2L ; /* TIMER 2 - LOW BYTE */
|
||||
__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
|
||||
__sfr __at (0xCD) TMR2H ; /* TIMER 2 - HIGH BYTE */
|
||||
__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
|
||||
__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
|
||||
__sfr __at (0xD4) P0SKIP ; /* PORT 0 SKIP */
|
||||
__sfr __at (0xD5) P1SKIP ; /* PORT 1 SKIP */
|
||||
__sfr __at (0xD6) P2SKIP ; /* PORT 2 SKIP */
|
||||
__sfr __at (0xD7) USB0XCN ; /* USB0 TRANSCEIVER CONTROL */
|
||||
__sfr __at (0xD8) PCA0CN ; /* PCA CONTROL */
|
||||
__sfr __at (0xD9) PCA0MD ; /* PCA MODE */
|
||||
__sfr __at (0xDA) PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
|
||||
__sfr __at (0xDB) PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
|
||||
__sfr __at (0xDC) PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
|
||||
__sfr __at (0xDD) PCA0CPM3 ; /* PCA MODULE 3 MODE REGISTER */
|
||||
__sfr __at (0xDE) PCA0CPM4 ; /* PCA MODULE 4 MODE REGISTER */
|
||||
__sfr __at (0xE0) ACC ; /* ACCUMULATOR */
|
||||
__sfr __at (0xE1) XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
|
||||
__sfr __at (0xE2) XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
|
||||
__sfr __at (0xE4) IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
|
||||
__sfr __at (0xE4) INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
|
||||
__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
|
||||
__sfr __at (0xE7) EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
|
||||
__sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */
|
||||
__sfr __at (0xE9) PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
|
||||
__sfr __at (0xEA) PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
|
||||
__sfr __at (0xEB) PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
|
||||
__sfr __at (0xEC) PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
|
||||
__sfr __at (0xED) PCA0CPL3 ; /* PCA CAPTURE 3 LOW */
|
||||
__sfr __at (0xEE) PCA0CPH3 ; /* PCA CAPTURE 3 HIGH */
|
||||
__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
|
||||
__sfr __at (0xF0) B ; /* B REGISTER */
|
||||
__sfr __at (0xF1) P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF1) P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF2) P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF2) P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF3) P2MODE ; /* PORT 2 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF3) P2MDIN ; /* PORT 2 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF4) P3MODE ; /* PORT 3 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF4) P3MDIN ; /* PORT 3 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
|
||||
__sfr __at (0xF7) EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
|
||||
__sfr __at (0xF8) SPI0CN ; /* SPI0 CONTROL */
|
||||
__sfr __at (0xF9) PCA0L ; /* PCA COUNTER LOW */
|
||||
__sfr __at (0xFA) PCA0H ; /* PCA COUNTER HIGH */
|
||||
__sfr __at (0xFB) PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
|
||||
__sfr __at (0xFC) PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
|
||||
__sfr __at (0xFD) PCA0CPL4 ; /* PCA CAPTURE 4 LOW */
|
||||
__sfr __at (0xFE) PCA0CPH4 ; /* PCA CAPTURE 4 HIGH */
|
||||
__sfr __at (0xFF) VDM0CN ; /* VDD MONITOR CONTROL */
|
||||
|
||||
|
||||
/* WORD/DWORD Registers */
|
||||
|
||||
__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
|
||||
__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
|
||||
__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
|
||||
__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
|
||||
__sfr16 __at (0xCBCA) TMR2RL ; /* TIMER 2 CAPTURE REGISTER WORD */
|
||||
__sfr16 __at (0x9594) TMR3 ; /* TIMER 3 COUNTER */
|
||||
__sfr16 __at (0x9392) TMR3RL ; /* TIMER 3 CAPTURE REGISTER WORD */
|
||||
__sfr16 __at (0xBEBD) ADC0 ; /* ADC 0 DATA WORD */
|
||||
__sfr16 __at (0xC4C3) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */
|
||||
__sfr16 __at (0xC6C5) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */
|
||||
__sfr16 __at (0xFAF9) PCA0 ; /* PCA COUNTER */
|
||||
__sfr16 __at (0xFCFB) PCA0CP0 ; /* PCA CAPTURE 0 WORD */
|
||||
__sfr16 __at (0xEAE9) PCA0CP1 ; /* PCA CAPTURE 1 WORD */
|
||||
__sfr16 __at (0xECEB) PCA0CP2 ; /* PCA CAPTURE 2 WORD */
|
||||
__sfr16 __at (0xEEED) PCA0CP3 ; /* PCA CAPTURE 3 WORD */
|
||||
__sfr16 __at (0xFEFD) PCA0CP4 ; /* PCA CAPTURE 4 WORD */
|
||||
|
||||
|
||||
/* BIT Registers */
|
||||
|
||||
/* P0 0x80 */
|
||||
__sbit __at (0x80) P0_0 ;
|
||||
__sbit __at (0x81) P0_1 ;
|
||||
__sbit __at (0x82) P0_2 ;
|
||||
__sbit __at (0x83) P0_3 ;
|
||||
__sbit __at (0x84) P0_4 ;
|
||||
__sbit __at (0x85) P0_5 ;
|
||||
__sbit __at (0x86) P0_6 ;
|
||||
__sbit __at (0x87) P0_7 ;
|
||||
|
||||
/* TCON 0x88 */
|
||||
__sbit __at (0x88) IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
|
||||
__sbit __at (0x89) IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
|
||||
__sbit __at (0x8A) IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
|
||||
__sbit __at (0x8B) IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
|
||||
__sbit __at (0x8C) TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
|
||||
__sbit __at (0x8D) TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
|
||||
__sbit __at (0x8E) TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
|
||||
__sbit __at (0x8F) TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
|
||||
|
||||
/* P1 0x90 */
|
||||
__sbit __at (0x90) P1_0 ;
|
||||
__sbit __at (0x91) P1_1 ;
|
||||
__sbit __at (0x92) P1_2 ;
|
||||
__sbit __at (0x93) P1_3 ;
|
||||
__sbit __at (0x94) P1_4 ;
|
||||
__sbit __at (0x95) P1_5 ;
|
||||
__sbit __at (0x96) P1_6 ;
|
||||
__sbit __at (0x97) P1_7 ;
|
||||
|
||||
/* SCON 0x98 */
|
||||
__sbit __at (0x98) RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
|
||||
__sbit __at (0x98) RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
|
||||
__sbit __at (0x99) TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
|
||||
__sbit __at (0x99) TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
|
||||
__sbit __at (0x9A) RB8 ; /* SCON.2 - RECEIVE BIT 8 */
|
||||
__sbit __at (0x9A) RB80 ; /* SCON.2 - RECEIVE BIT 8 */
|
||||
__sbit __at (0x9B) TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
|
||||
__sbit __at (0x9B) TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
|
||||
__sbit __at (0x9C) REN ; /* SCON.4 - RECEIVE ENABLE */
|
||||
__sbit __at (0x9C) REN0 ; /* SCON.4 - RECEIVE ENABLE */
|
||||
__sbit __at (0x9D) SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
|
||||
__sbit __at (0x9D) MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
|
||||
__sbit __at (0x9F) SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
|
||||
__sbit __at (0x9F) S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
|
||||
|
||||
/* P2 0xA0 */
|
||||
__sbit __at (0xA0) P2_0 ;
|
||||
__sbit __at (0xA1) P2_1 ;
|
||||
__sbit __at (0xA2) P2_2 ;
|
||||
__sbit __at (0xA3) P2_3 ;
|
||||
__sbit __at (0xA4) P2_4 ;
|
||||
__sbit __at (0xA5) P2_5 ;
|
||||
__sbit __at (0xA6) P2_6 ;
|
||||
__sbit __at (0xA7) P2_7 ;
|
||||
|
||||
/* IE 0xA8 */
|
||||
__sbit __at (0xA8) EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
|
||||
__sbit __at (0xA9) ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAA) EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
|
||||
__sbit __at (0xAB) ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAC) ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
|
||||
__sbit __at (0xAC) ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
|
||||
__sbit __at (0xAD) ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAE) ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAF) EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
|
||||
|
||||
/* P3 0xB0 */
|
||||
__sbit __at (0xB0) P3_0 ;
|
||||
__sbit __at (0xB1) P3_1 ;
|
||||
__sbit __at (0xB2) P3_2 ;
|
||||
__sbit __at (0xB3) P3_3 ;
|
||||
__sbit __at (0xB4) P3_4 ;
|
||||
__sbit __at (0xB5) P3_5 ;
|
||||
__sbit __at (0xB6) P3_6 ;
|
||||
__sbit __at (0xB7) P3_7 ;
|
||||
|
||||
/* IP 0xB8 */
|
||||
__sbit __at (0xB8) PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
|
||||
__sbit __at (0xB9) PT0 ; /* IP.1 - TIMER 0 PRIORITY */
|
||||
__sbit __at (0xBA) PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
|
||||
__sbit __at (0xBB) PT1 ; /* IP.3 - TIMER 1 PRIORITY */
|
||||
__sbit __at (0xBC) PS ; /* IP.4 - SERIAL PORT PRIORITY */
|
||||
__sbit __at (0xBC) PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
|
||||
__sbit __at (0xBD) PT2 ; /* IP.5 - TIMER 2 PRIORITY */
|
||||
__sbit __at (0xBE) PSPI0 ; /* IP.6 - SPI0 PRIORITY */
|
||||
|
||||
/* SMB0CN 0xC0 */
|
||||
__sbit __at (0xC0) SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
|
||||
__sbit __at (0xC1) ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
|
||||
__sbit __at (0xC2) ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
|
||||
__sbit __at (0xC3) ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
|
||||
__sbit __at (0xC4) STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
|
||||
__sbit __at (0xC5) STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
|
||||
__sbit __at (0xC6) TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
|
||||
__sbit __at (0xC7) MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
|
||||
|
||||
/* TMR2CN 0xC8 */
|
||||
__sbit __at (0xC8) T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
|
||||
__sbit __at (0xCA) TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
|
||||
__sbit __at (0xCB) T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
|
||||
__sbit __at (0xCC) T2SOF ; /* TMR2CN.4 - TIMER 2 START_OF_FRAME CAPTURE ENA */
|
||||
__sbit __at (0xCD) TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
|
||||
__sbit __at (0xCE) TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
|
||||
__sbit __at (0xCF) TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
|
||||
__sbit __at (0xCF) TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
|
||||
|
||||
/* PSW 0xD0 */
|
||||
__sbit __at (0xD0) PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
|
||||
__sbit __at (0xD1) F1 ; /* PSW.1 - FLAG 1 */
|
||||
__sbit __at (0xD2) OV ; /* PSW.2 - OVERFLOW FLAG */
|
||||
__sbit __at (0xD3) RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
|
||||
__sbit __at (0xD4) RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
|
||||
__sbit __at (0xD5) F0 ; /* PSW.5 - FLAG 0 */
|
||||
__sbit __at (0xD6) AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
|
||||
__sbit __at (0xD7) CY ; /* PSW.7 - CARRY FLAG */
|
||||
|
||||
/* PCA0CN 0xD8 */
|
||||
__sbit __at (0xD8) CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
|
||||
__sbit __at (0xD9) CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
|
||||
__sbit __at (0xDA) CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
|
||||
__sbit __at (0xDB) CCF3 ; /* PCA0CN.3 - PCA MODULE 3 CAPTURE/COMPARE FLAG */
|
||||
__sbit __at (0xDC) CCF4 ; /* PCA0CN.4 - PCA MODULE 4 CAPTURE/COMPARE FLAG */
|
||||
__sbit __at (0xDE) CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
|
||||
__sbit __at (0xDF) CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
|
||||
|
||||
/* ADC0CN 0xE8 */
|
||||
__sbit __at (0xE8) AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
|
||||
__sbit __at (0xE9) AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
|
||||
__sbit __at (0xEA) AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
|
||||
__sbit __at (0xEB) AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
|
||||
__sbit __at (0xEC) AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
|
||||
__sbit __at (0xED) AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
|
||||
__sbit __at (0xEE) AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */
|
||||
__sbit __at (0xEF) AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */
|
||||
|
||||
/* SPI0CN 0xF8 */
|
||||
__sbit __at (0xF8) SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */
|
||||
__sbit __at (0xF9) TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
|
||||
__sbit __at (0xFA) NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
|
||||
__sbit __at (0xFB) NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
|
||||
__sbit __at (0xFC) RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
|
||||
__sbit __at (0xFD) MODF ; /* SPI0CN.5 - MODE FAULT FLAG */
|
||||
__sbit __at (0xFE) WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */
|
||||
__sbit __at (0xFF) SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
|
||||
|
||||
|
||||
/* Predefined SFR Bit Masks */
|
||||
|
||||
#define PCON_IDLE 0x01 /* PCON */
|
||||
#define PCON_STOP 0x02 /* PCON */
|
||||
#define T1M 0x08 /* CKCON */
|
||||
#define PSWE 0x01 /* PSCTL */
|
||||
#define PSEE 0x02 /* PSCTL */
|
||||
#define ECP0 0x20 /* EIE1 */
|
||||
#define ECP1 0x40 /* EIE1 */
|
||||
#define PORSF 0x02 /* RSTSRC */
|
||||
#define SWRSF 0x10 /* RSTSRC */
|
||||
#define ECCF 0x01 /* PCA0CPMn */
|
||||
#define PWM 0x02 /* PCA0CPMn */
|
||||
#define TOG 0x04 /* PCA0CPMn */
|
||||
#define MAT 0x08 /* PCA0CPMn */
|
||||
#define CAPN 0x10 /* PCA0CPMn */
|
||||
#define CAPP 0x20 /* PCA0CPMn */
|
||||
#define ECOM 0x40 /* PCA0CPMn */
|
||||
#define PWM16 0x80 /* PCA0CPMn */
|
||||
#define CP0E 0x10 /* XBR0 */
|
||||
#define CP0OEN 0x10 /* XBR0 */
|
||||
#define CP0AE 0x20 /* XBR0 */
|
||||
#define CP0AOEN 0x20 /* XBR0 */
|
||||
#define CP1E 0x40 /* XBR0 */
|
||||
#define CP1AE 0x80 /* XBR0 */
|
||||
|
||||
#endif
|
||||
183
lib/mcs51/C8051F326.h
Normal file
183
lib/mcs51/C8051F326.h
Normal file
@@ -0,0 +1,183 @@
|
||||
/*-------------------------------------------------------------------------
|
||||
C8051F326.h - Register Declarations for the Cygnal/SiLabs C8051F326/7
|
||||
Processor Range
|
||||
|
||||
Copyright (C) 2006, Maarten Brock, sourceforge.brock@dse.nl
|
||||
|
||||
This library is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the
|
||||
Free Software Foundation; either version 2, or (at your option) any
|
||||
later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this library; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
|
||||
MA 02110-1301, USA.
|
||||
|
||||
As a special exception, if you link this library with other files,
|
||||
some of which are compiled with SDCC, to produce an executable,
|
||||
this library does not by itself cause the resulting executable to
|
||||
be covered by the GNU General Public License. This exception does
|
||||
not however invalidate any other reasons why the executable file
|
||||
might be covered by the GNU General Public License.
|
||||
-------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef C8051F326_H
|
||||
#define C8051F326_H
|
||||
|
||||
|
||||
/* BYTE Registers */
|
||||
__sfr __at (0x80) P0 ; /* PORT 0 */
|
||||
__sfr __at (0x81) SP ; /* STACK POINTER */
|
||||
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
|
||||
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
|
||||
__sfr __at (0x87) PCON ; /* POWER CONTROL */
|
||||
__sfr __at (0x88) TCON ; /* TIMER CONTROL */
|
||||
__sfr __at (0x89) TMOD ; /* TIMER MODE */
|
||||
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
|
||||
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
|
||||
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
|
||||
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
|
||||
__sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
|
||||
__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
|
||||
__sfr __at (0x91) SBCON0 ; /* BAUDRATE GENERATOR 0 CONTROL */
|
||||
__sfr __at (0x93) SBRLL0 ; /* BAUDRATE GENERATOR 0 RELOAD VALUE - LOW BYTE */
|
||||
__sfr __at (0x94) SBRLH0 ; /* BAUDRATE GENERATOR 0 RELOAD VALUE - HIGH BYTE */
|
||||
__sfr __at (0x96) USB0ADR ; /* USB0 INDIRECT ADDRESS REGISTER */
|
||||
__sfr __at (0x97) USB0DAT ; /* USB0 DATA REGISTER */
|
||||
__sfr __at (0x98) SCON ; /* UART0 CONTROL */
|
||||
__sfr __at (0x98) SCON0 ; /* UART0 CONTROL */
|
||||
__sfr __at (0x99) SBUF ; /* UART0 BUFFER */
|
||||
__sfr __at (0x99) SBUF0 ; /* UART0 BUFFER */
|
||||
__sfr __at (0x9A) SMOD0 ; /* UART0 MODE */
|
||||
__sfr __at (0xA0) P2 ; /* PORT 2 */
|
||||
__sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA7) P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
|
||||
__sfr __at (0xA9) CLKSEL ; /* SYSTEM CLOCK SELECT */
|
||||
__sfr __at (0xAA) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
|
||||
__sfr __at (0xAA) _XPAGE ; /* XDATA/PDATA PAGE */
|
||||
__sfr __at (0xB0) P3 ; /* PORT 3 */
|
||||
__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at (0xB3) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
|
||||
__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
|
||||
__sfr __at (0xB7) FLKEY ; /* FLASH ACESS LIMIT */
|
||||
__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
|
||||
__sfr __at (0xB9) CLKMUL ; /* CLOCK MULTIPLIER CONTROL REGISTER */
|
||||
__sfr __at (0xC9) REG0CN ; /* VOLTAGE REGULATOR CONTROL */
|
||||
__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
|
||||
__sfr __at (0xD7) USB0XCN ; /* USB0 TRANSCEIVER CONTROL */
|
||||
__sfr __at (0xE0) ACC ; /* ACCUMULATOR */
|
||||
__sfr __at (0xE2) GPIOCN ; /* GLOBAL PORT I/O CONTROL */
|
||||
__sfr __at (0xE3) OSCLCN ; /* LOW-FREQUENCY OSCILLATOR CONTROL */
|
||||
__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
|
||||
__sfr __at (0xE7) EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
|
||||
__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
|
||||
__sfr __at (0xF0) B ; /* B REGISTER */
|
||||
__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
|
||||
__sfr __at (0xF7) EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
|
||||
__sfr __at (0xFF) VDM0CN ; /* VDD MONITOR CONTROL */
|
||||
|
||||
|
||||
/* WORD/DWORD Registers */
|
||||
|
||||
__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
|
||||
__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
|
||||
__sfr16 __at (0x9493) SBRL0 ; /* BAUDRATE GENERATOR 0 RELOAD VALUE WORD */
|
||||
|
||||
|
||||
/* BIT Registers */
|
||||
|
||||
/* P0 0x80 */
|
||||
__sbit __at (0x80) P0_0 ;
|
||||
__sbit __at (0x81) P0_1 ;
|
||||
__sbit __at (0x82) P0_2 ;
|
||||
__sbit __at (0x83) P0_3 ;
|
||||
__sbit __at (0x84) P0_4 ;
|
||||
__sbit __at (0x85) P0_5 ;
|
||||
__sbit __at (0x86) P0_6 ;
|
||||
__sbit __at (0x87) P0_7 ;
|
||||
|
||||
/* TCON 0x88 */
|
||||
__sbit __at (0x88) IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
|
||||
__sbit __at (0x89) IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
|
||||
__sbit __at (0x8A) IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
|
||||
__sbit __at (0x8B) IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
|
||||
__sbit __at (0x8C) TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
|
||||
__sbit __at (0x8D) TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
|
||||
__sbit __at (0x8E) TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
|
||||
__sbit __at (0x8F) TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
|
||||
|
||||
/* SCON 0x98 */
|
||||
__sbit __at (0x98) RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
|
||||
__sbit __at (0x98) RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
|
||||
__sbit __at (0x99) TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
|
||||
__sbit __at (0x99) TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
|
||||
__sbit __at (0x9A) RB8 ; /* SCON.2 - RECEIVE BIT 8 */
|
||||
__sbit __at (0x9A) RBX0 ; /* SCON.2 - EXTRA RECEIVE BIT */
|
||||
__sbit __at (0x9B) TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
|
||||
__sbit __at (0x9B) TBX0 ; /* SCON.3 - EXTRA TRANSMIT BIT */
|
||||
__sbit __at (0x9C) REN ; /* SCON.4 - RECEIVE ENABLE */
|
||||
__sbit __at (0x9C) REN0 ; /* SCON.4 - RECEIVE ENABLE */
|
||||
__sbit __at (0x9E) PERR0 ; /* SCON.6 - PARITY ERROR FLAG */
|
||||
__sbit __at (0x9F) OVR0 ; /* SCON.7 - RECEIVE FIFO OVERRUN FLAG */
|
||||
|
||||
/* P2 0xA0 */
|
||||
__sbit __at (0xA0) P2_0 ;
|
||||
__sbit __at (0xA1) P2_1 ;
|
||||
__sbit __at (0xA2) P2_2 ;
|
||||
__sbit __at (0xA3) P2_3 ;
|
||||
__sbit __at (0xA4) P2_4 ;
|
||||
__sbit __at (0xA5) P2_5 ;
|
||||
|
||||
/* IE 0xA8 */
|
||||
__sbit __at (0xA8) EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
|
||||
__sbit __at (0xA9) ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAA) EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
|
||||
__sbit __at (0xAB) ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAC) ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
|
||||
__sbit __at (0xAC) ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
|
||||
__sbit __at (0xAF) EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
|
||||
|
||||
/* P3 0xB0 */
|
||||
__sbit __at (0xB0) P3_0 ;
|
||||
|
||||
/* IP 0xB8 */
|
||||
__sbit __at (0xB8) PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
|
||||
__sbit __at (0xB9) PT0 ; /* IP.1 - TIMER 0 PRIORITY */
|
||||
__sbit __at (0xBA) PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
|
||||
__sbit __at (0xBB) PT1 ; /* IP.3 - TIMER 1 PRIORITY */
|
||||
__sbit __at (0xBC) PS ; /* IP.4 - SERIAL PORT PRIORITY */
|
||||
__sbit __at (0xBC) PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
|
||||
|
||||
/* PSW 0xD0 */
|
||||
__sbit __at (0xD0) PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
|
||||
__sbit __at (0xD1) F1 ; /* PSW.1 - FLAG 1 */
|
||||
__sbit __at (0xD2) OV ; /* PSW.2 - OVERFLOW FLAG */
|
||||
__sbit __at (0xD3) RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
|
||||
__sbit __at (0xD4) RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
|
||||
__sbit __at (0xD5) F0 ; /* PSW.5 - FLAG 0 */
|
||||
__sbit __at (0xD6) AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
|
||||
__sbit __at (0xD7) CY ; /* PSW.7 - CARRY FLAG */
|
||||
|
||||
|
||||
/* Predefined SFR Bit Masks */
|
||||
|
||||
#define PCON_IDLE 0x01 /* PCON */
|
||||
#define PCON_STOP 0x02 /* PCON */
|
||||
#define T0M 0x04 /* CKCON */
|
||||
#define T1M 0x08 /* CKCON */
|
||||
#define PSWE 0x01 /* PSCTL */
|
||||
#define PSEE 0x02 /* PSCTL */
|
||||
#define EUSB0 0x02 /* EIE1 */
|
||||
#define EVBUS 0x01 /* EIE2 */
|
||||
#define PORSF 0x02 /* RSTSRC */
|
||||
#define SWRSF 0x10 /* RSTSRC */
|
||||
|
||||
#endif
|
||||
319
lib/mcs51/C8051F330.h
Normal file
319
lib/mcs51/C8051F330.h
Normal file
@@ -0,0 +1,319 @@
|
||||
/*-------------------------------------------------------------------------
|
||||
C8051F330.h - Register Declarations for the Cygnal/SiLabs C8051F33x
|
||||
Processor Range
|
||||
|
||||
Copyright (C) 2004, Maarten Brock, sourceforge.brock@dse.nl
|
||||
|
||||
This library is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the
|
||||
Free Software Foundation; either version 2, or (at your option) any
|
||||
later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this library; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
|
||||
MA 02110-1301, USA.
|
||||
|
||||
As a special exception, if you link this library with other files,
|
||||
some of which are compiled with SDCC, to produce an executable,
|
||||
this library does not by itself cause the resulting executable to
|
||||
be covered by the GNU General Public License. This exception does
|
||||
not however invalidate any other reasons why the executable file
|
||||
might be covered by the GNU General Public License.
|
||||
-------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef C8051F330_H
|
||||
#define C8051F330_H
|
||||
|
||||
|
||||
/* BYTE Registers */
|
||||
|
||||
__sfr __at (0x80) P0 ; /* PORT 0 */
|
||||
__sfr __at (0x81) SP ; /* STACK POINTER */
|
||||
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
|
||||
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
|
||||
__sfr __at (0x87) PCON ; /* POWER CONTROL */
|
||||
__sfr __at (0x88) TCON ; /* TIMER CONTROL */
|
||||
__sfr __at (0x89) TMOD ; /* TIMER MODE */
|
||||
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
|
||||
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
|
||||
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
|
||||
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
|
||||
__sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
|
||||
__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
|
||||
__sfr __at (0x90) P1 ; /* PORT 1 */
|
||||
__sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */
|
||||
__sfr __at (0x92) TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at (0x93) TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */
|
||||
__sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */
|
||||
__sfr __at (0x96) IDA0L ; /* CURRENT MODE DAC 0 - LOW BYTE */
|
||||
__sfr __at (0x97) IDA0H ; /* CURRENT MODE DAC 0 - HIGH BYTE */
|
||||
__sfr __at (0x98) SCON ; /* SERIAL PORT CONTROL */
|
||||
__sfr __at (0x98) SCON0 ; /* SERIAL PORT CONTROL */
|
||||
__sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
|
||||
__sfr __at (0x99) SBUF0 ; /* SERIAL PORT BUFFER */
|
||||
__sfr __at (0x9B) CPT0CN ; /* COMPARATOR 0 CONTROL */
|
||||
__sfr __at (0x9D) CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
|
||||
__sfr __at (0x9F) CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
|
||||
__sfr __at (0xA0) P2 ; /* PORT 2 */
|
||||
__sfr __at (0xA1) SPI0CFG ; /* SPI0 CONFIGURATION */
|
||||
__sfr __at (0xA2) SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */
|
||||
__sfr __at (0xA3) SPI0DAT ; /* SPI0 DATA */
|
||||
__sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA5) P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
|
||||
__sfr __at (0xA9) CLKSEL ; /* SYSTEM CLOCK SELECT */
|
||||
__sfr __at (0xAA) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
|
||||
__sfr __at (0xAA) _XPAGE ; /* XDATA/PDATA PAGE */
|
||||
__sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at (0xB3) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
|
||||
__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
|
||||
__sfr __at (0xB7) FLKEY ; /* FLASH ACESS LIMIT */
|
||||
__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
|
||||
__sfr __at (0xB9) IDA0CN ; /* CURRENT MODE DAC 0 - CONTROL */
|
||||
__sfr __at (0xBA) AMX0N ; /* ADC 0 MUX NEGATIVE CHANNEL SELECTION */
|
||||
__sfr __at (0xBB) AMX0P ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */
|
||||
__sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */
|
||||
__sfr __at (0xBD) ADC0L ; /* ADC 0 DATA WORD LSB */
|
||||
__sfr __at (0xBE) ADC0H ; /* ADC 0 DATA WORD MSB */
|
||||
__sfr __at (0xC0) SMB0CN ; /* SMBUS CONTROL */
|
||||
__sfr __at (0xC1) SMB0CF ; /* SMBUS CONFIGURATION */
|
||||
__sfr __at (0xC2) SMB0DAT ; /* SMBUS DATA */
|
||||
__sfr __at (0xC3) ADC0GTL ; /* ADC 0 GREATER-THAN LOW BYTE */
|
||||
__sfr __at (0xC4) ADC0GTH ; /* ADC 0 GREATER-THAN HIGH BYTE */
|
||||
__sfr __at (0xC5) ADC0LTL ; /* ADC 0 LESS-THAN LOW BYTE */
|
||||
__sfr __at (0xC6) ADC0LTH ; /* ADC 0 LESS-THAN HIGH BYTE */
|
||||
__sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
|
||||
__sfr __at (0xC8) TMR2CN ; /* TIMER 2 CONTROL */
|
||||
__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at (0xCA) TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xCB) TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
|
||||
__sfr __at (0xCC) TMR2L ; /* TIMER 2 - LOW BYTE */
|
||||
__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
|
||||
__sfr __at (0xCD) TMR2H ; /* TIMER 2 - HIGH BYTE */
|
||||
__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
|
||||
__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
|
||||
__sfr __at (0xD4) P0SKIP ; /* PORT 0 SKIP */
|
||||
__sfr __at (0xD5) P1SKIP ; /* PORT 1 SKIP */
|
||||
__sfr __at (0xD8) PCA0CN ; /* PCA CONTROL */
|
||||
__sfr __at (0xD9) PCA0MD ; /* PCA MODE */
|
||||
__sfr __at (0xDA) PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
|
||||
__sfr __at (0xDB) PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
|
||||
__sfr __at (0xDC) PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
|
||||
__sfr __at (0xE0) ACC ; /* ACCUMULATOR */
|
||||
__sfr __at (0xE1) XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
|
||||
__sfr __at (0xE2) XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
|
||||
__sfr __at (0xE3) OSCLCN ; /* LOW-FREQUENCY OSCILLATOR CONTROL */
|
||||
__sfr __at (0xE4) IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
|
||||
__sfr __at (0xE4) INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
|
||||
__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
|
||||
__sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */
|
||||
__sfr __at (0xE9) PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
|
||||
__sfr __at (0xEA) PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
|
||||
__sfr __at (0xEB) PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
|
||||
__sfr __at (0xEC) PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
|
||||
__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
|
||||
__sfr __at (0xF0) B ; /* B REGISTER */
|
||||
__sfr __at (0xF1) P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF1) P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF2) P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF2) P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
|
||||
__sfr __at (0xF8) SPI0CN ; /* SPI0 CONTROL */
|
||||
__sfr __at (0xF9) PCA0L ; /* PCA COUNTER LOW */
|
||||
__sfr __at (0xFA) PCA0H ; /* PCA COUNTER HIGH */
|
||||
__sfr __at (0xFB) PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
|
||||
__sfr __at (0xFC) PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
|
||||
__sfr __at (0xFF) VDM0CN ; /* VDD MONITOR CONTROL */
|
||||
|
||||
|
||||
/* WORD/DWORD Registers */
|
||||
|
||||
__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
|
||||
__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
|
||||
__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
|
||||
__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
|
||||
__sfr16 __at (0xCBCA) TMR2RL ; /* TIMER 2 CAPTURE REGISTER WORD */
|
||||
__sfr16 __at (0x9594) TMR3 ; /* TIMER 3 COUNTER */
|
||||
__sfr16 __at (0x9392) TMR3RL ; /* TIMER 3 CAPTURE REGISTER WORD */
|
||||
__sfr16 __at (0x9796) IDA0 ; /* CURRENT MODE DAC 0 DATA WORD */
|
||||
__sfr16 __at (0xBEBD) ADC0 ; /* ADC 0 DATA WORD */
|
||||
__sfr16 __at (0xC4C3) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */
|
||||
__sfr16 __at (0xC6C5) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */
|
||||
__sfr16 __at (0xFAF9) PCA0 ; /* PCA COUNTER */
|
||||
__sfr16 __at (0xFCFB) PCA0CP0 ; /* PCA CAPTURE 0 WORD */
|
||||
__sfr16 __at (0xEAE9) PCA0CP1 ; /* PCA CAPTURE 1 WORD */
|
||||
__sfr16 __at (0xECEB) PCA0CP2 ; /* PCA CAPTURE 2 WORD */
|
||||
|
||||
|
||||
/* BIT Registers */
|
||||
|
||||
/* P0 0x80 */
|
||||
__sbit __at (0x80) P0_0 ;
|
||||
__sbit __at (0x81) P0_1 ;
|
||||
__sbit __at (0x82) P0_2 ;
|
||||
__sbit __at (0x83) P0_3 ;
|
||||
__sbit __at (0x84) P0_4 ;
|
||||
__sbit __at (0x85) P0_5 ;
|
||||
__sbit __at (0x86) P0_6 ;
|
||||
__sbit __at (0x87) P0_7 ;
|
||||
|
||||
/* TCON 0x88 */
|
||||
__sbit __at (0x88) IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
|
||||
__sbit __at (0x89) IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
|
||||
__sbit __at (0x8A) IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
|
||||
__sbit __at (0x8B) IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
|
||||
__sbit __at (0x8C) TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
|
||||
__sbit __at (0x8D) TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
|
||||
__sbit __at (0x8E) TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
|
||||
__sbit __at (0x8F) TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
|
||||
|
||||
/* P1 0x90 */
|
||||
__sbit __at (0x90) P1_0 ;
|
||||
__sbit __at (0x91) P1_1 ;
|
||||
__sbit __at (0x92) P1_2 ;
|
||||
__sbit __at (0x93) P1_3 ;
|
||||
__sbit __at (0x94) P1_4 ;
|
||||
__sbit __at (0x95) P1_5 ;
|
||||
__sbit __at (0x96) P1_6 ;
|
||||
__sbit __at (0x97) P1_7 ;
|
||||
|
||||
/* SCON 0x98 */
|
||||
__sbit __at (0x98) RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
|
||||
__sbit __at (0x98) RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
|
||||
__sbit __at (0x99) TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
|
||||
__sbit __at (0x99) TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
|
||||
__sbit __at (0x9A) RB8 ; /* SCON.2 - RECEIVE BIT 8 */
|
||||
__sbit __at (0x9A) RB80 ; /* SCON.2 - RECEIVE BIT 8 */
|
||||
__sbit __at (0x9B) TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
|
||||
__sbit __at (0x9B) TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
|
||||
__sbit __at (0x9C) REN ; /* SCON.4 - RECEIVE ENABLE */
|
||||
__sbit __at (0x9C) REN0 ; /* SCON.4 - RECEIVE ENABLE */
|
||||
__sbit __at (0x9D) SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
|
||||
__sbit __at (0x9D) MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
|
||||
__sbit __at (0x9F) SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
|
||||
__sbit __at (0x9F) S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
|
||||
|
||||
/* P2 0xA0 */
|
||||
__sbit __at (0xA0) P2_0 ;
|
||||
__sbit __at (0xA1) P2_1 ;
|
||||
__sbit __at (0xA2) P2_2 ;
|
||||
__sbit __at (0xA3) P2_3 ;
|
||||
__sbit __at (0xA4) P2_4 ;
|
||||
__sbit __at (0xA5) P2_5 ;
|
||||
__sbit __at (0xA6) P2_6 ;
|
||||
__sbit __at (0xA7) P2_7 ;
|
||||
|
||||
/* IE 0xA8 */
|
||||
__sbit __at (0xA8) EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
|
||||
__sbit __at (0xA9) ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAA) EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
|
||||
__sbit __at (0xAB) ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAC) ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
|
||||
__sbit __at (0xAC) ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
|
||||
__sbit __at (0xAD) ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAE) ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAF) EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
|
||||
|
||||
/* IP 0xB8 */
|
||||
__sbit __at (0xB8) PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
|
||||
__sbit __at (0xB9) PT0 ; /* IP.1 - TIMER 0 PRIORITY */
|
||||
__sbit __at (0xBA) PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
|
||||
__sbit __at (0xBB) PT1 ; /* IP.3 - TIMER 1 PRIORITY */
|
||||
__sbit __at (0xBC) PS ; /* IP.4 - SERIAL PORT PRIORITY */
|
||||
__sbit __at (0xBC) PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
|
||||
__sbit __at (0xBD) PT2 ; /* IP.5 - TIMER 2 PRIORITY */
|
||||
__sbit __at (0xBE) PSPI0 ; /* IP.6 - SPI0 PRIORITY */
|
||||
|
||||
/* SMB0CN 0xC0 */
|
||||
__sbit __at (0xC0) SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
|
||||
__sbit __at (0xC1) ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
|
||||
__sbit __at (0xC2) ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
|
||||
__sbit __at (0xC3) ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
|
||||
__sbit __at (0xC4) STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
|
||||
__sbit __at (0xC5) STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
|
||||
__sbit __at (0xC6) TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
|
||||
__sbit __at (0xC7) MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
|
||||
|
||||
/* TMR2CN 0xC8 */
|
||||
__sbit __at (0xC8) T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
|
||||
__sbit __at (0xCA) TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
|
||||
__sbit __at (0xCB) T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
|
||||
__sbit __at (0xCC) TF2CEN ; /* TMR2CN.4 - TIMER 2 LOW-FREQ OSC CAPTURE ENABLE*/
|
||||
__sbit __at (0xCD) TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
|
||||
__sbit __at (0xCE) TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
|
||||
__sbit __at (0xCF) TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
|
||||
__sbit __at (0xCF) TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
|
||||
|
||||
/* PSW 0xD0 */
|
||||
__sbit __at (0xD0) PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
|
||||
__sbit __at (0xD1) F1 ; /* PSW.1 - FLAG 1 */
|
||||
__sbit __at (0xD2) OV ; /* PSW.2 - OVERFLOW FLAG */
|
||||
__sbit __at (0xD3) RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
|
||||
__sbit __at (0xD4) RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
|
||||
__sbit __at (0xD5) F0 ; /* PSW.5 - FLAG 0 */
|
||||
__sbit __at (0xD6) AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
|
||||
__sbit __at (0xD7) CY ; /* PSW.7 - CARRY FLAG */
|
||||
|
||||
/* PCA0CN 0xD8 */
|
||||
__sbit __at (0xD8) CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
|
||||
__sbit __at (0xD9) CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
|
||||
__sbit __at (0xDA) CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
|
||||
__sbit __at (0xDE) CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
|
||||
__sbit __at (0xDF) CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
|
||||
|
||||
/* ADC0CN 0xE8 */
|
||||
__sbit __at (0xE8) AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
|
||||
__sbit __at (0xE9) AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
|
||||
__sbit __at (0xEA) AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
|
||||
__sbit __at (0xEB) AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
|
||||
__sbit __at (0xEC) AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
|
||||
__sbit __at (0xED) AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
|
||||
__sbit __at (0xEE) AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */
|
||||
__sbit __at (0xEF) AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */
|
||||
|
||||
/* SPI0CN 0xF8 */
|
||||
__sbit __at (0xF8) SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */
|
||||
__sbit __at (0xF9) TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
|
||||
__sbit __at (0xFA) NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
|
||||
__sbit __at (0xFB) NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
|
||||
__sbit __at (0xFC) RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
|
||||
__sbit __at (0xFD) MODF ; /* SPI0CN.5 - MODE FAULT FLAG */
|
||||
__sbit __at (0xFE) WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */
|
||||
__sbit __at (0xFF) SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
|
||||
|
||||
|
||||
/* Predefined SFR Bit Masks */
|
||||
|
||||
#define PCON_IDLE 0x01 /* PCON */
|
||||
#define PCON_STOP 0x02 /* PCON */
|
||||
#define T1M 0x08 /* CKCON */
|
||||
#define PSWE 0x01 /* PSCTL */
|
||||
#define PSEE 0x02 /* PSCTL */
|
||||
#define ECP0 0x20 /* EIE1 */
|
||||
#define PORSF 0x02 /* RSTSRC */
|
||||
#define SWRSF 0x10 /* RSTSRC */
|
||||
#define ECCF 0x01 /* PCA0CPMn */
|
||||
#define PWM 0x02 /* PCA0CPMn */
|
||||
#define TOG 0x04 /* PCA0CPMn */
|
||||
#define MAT 0x08 /* PCA0CPMn */
|
||||
#define CAPN 0x10 /* PCA0CPMn */
|
||||
#define CAPP 0x20 /* PCA0CPMn */
|
||||
#define ECOM 0x40 /* PCA0CPMn */
|
||||
#define PWM16 0x80 /* PCA0CPMn */
|
||||
#define CP0E 0x10 /* XBR0 */
|
||||
#define CP0OEN 0x10 /* XBR0 */
|
||||
#define CP0AE 0x20 /* XBR0 */
|
||||
#define CP0AOEN 0x20 /* XBR0 */
|
||||
|
||||
#endif
|
||||
347
lib/mcs51/C8051F336.h
Normal file
347
lib/mcs51/C8051F336.h
Normal file
@@ -0,0 +1,347 @@
|
||||
/*-------------------------------------------------------------------------
|
||||
C8051F336.h - Register Declarations for the SiLabs C8051F336/7/8/9
|
||||
Processor Range
|
||||
|
||||
Copyright (C) 2008, Steven Borley, steven.borley@partnerelectronics.com
|
||||
|
||||
This library is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the
|
||||
Free Software Foundation; either version 2, or (at your option) any
|
||||
later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this library; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
|
||||
MA 02110-1301, USA.
|
||||
|
||||
As a special exception, if you link this library with other files,
|
||||
some of which are compiled with SDCC, to produce an executable,
|
||||
this library does not by itself cause the resulting executable to
|
||||
be covered by the GNU General Public License. This exception does
|
||||
not however invalidate any other reasons why the executable file
|
||||
might be covered by the GNU General Public License.
|
||||
-------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef C8051F336_H
|
||||
#define C8051F336_H
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
/* BYTE Registers */
|
||||
|
||||
SFR( P0, 0x80 ) ; /* PORT 0 */
|
||||
SFR( SP, 0x81 ) ; /* STACK POINTER */
|
||||
SFR( DPL, 0x82 ) ; /* DATA POINTER - LOW BYTE */
|
||||
SFR( DPH, 0x83 ) ; /* DATA POINTER - HIGH BYTE */
|
||||
SFR( PCON, 0x87 ) ; /* POWER CONTROL */
|
||||
SFR( TCON, 0x88 ) ; /* TIMER CONTROL */
|
||||
SFR( TMOD, 0x89 ) ; /* TIMER MODE */
|
||||
SFR( TL0, 0x8A ) ; /* TIMER 0 - LOW BYTE */
|
||||
SFR( TL1, 0x8B ) ; /* TIMER 1 - LOW BYTE */
|
||||
SFR( TH0, 0x8C ) ; /* TIMER 0 - HIGH BYTE */
|
||||
SFR( TH1, 0x8D ) ; /* TIMER 1 - HIGH BYTE */
|
||||
SFR( CKCON, 0x8E ) ; /* CLOCK CONTROL */
|
||||
SFR( PSCTL, 0x8F ) ; /* PROGRAM STORE R/W CONTROL */
|
||||
SFR( P1, 0x90 ) ; /* PORT 1 */
|
||||
SFR( TMR3CN, 0x91 ) ; /* TIMER 3 CONTROL */
|
||||
SFR( TMR3RLL, 0x92 ) ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
|
||||
SFR( TMR3RLH, 0x93 ) ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
|
||||
SFR( TMR3L, 0x94 ) ; /* TIMER 3 - LOW BYTE */
|
||||
SFR( TMR3H, 0x95 ) ; /* TIMER 3 - HIGH BYTE */
|
||||
SFR( IDA0L, 0x96 ) ; /* CURRENT MODE DAC 0 - LOW BYTE */
|
||||
SFR( IDA0H, 0x97 ) ; /* CURRENT MODE DAC 0 - HIGH BYTE */
|
||||
SFR( SCON, 0x98 ) ; /* SERIAL PORT CONTROL */
|
||||
SFR( SCON0, 0x98 ) ; /* SERIAL PORT CONTROL */
|
||||
SFR( SBUF, 0x99 ) ; /* SERIAL PORT BUFFER */
|
||||
SFR( SBUF0, 0x99 ) ; /* SERIAL PORT BUFFER */
|
||||
SFR( CPT0CN, 0x9B ) ; /* COMPARATOR 0 CONTROL */
|
||||
SFR( CPT0MD, 0x9D ) ; /* COMPARATOR 0 MODE SELECTION */
|
||||
SFR( CPT0MX, 0x9F ) ; /* COMPARATOR 0 MUX SELECTION */
|
||||
SFR( P2, 0xA0 ) ; /* PORT 2 */
|
||||
SFR( SPI0CFG, 0xA1 ) ; /* SPI0 CONFIGURATION */
|
||||
SFR( SPI0CKR, 0xA2 ) ; /* SPI0 CLOCK RATE CONTROL */
|
||||
SFR( SPI0DAT, 0xA3 ) ; /* SPI0 DATA */
|
||||
SFR( P0MDOUT, 0xA4 ) ; /* PORT 0 OUTPUT MODE CONFIGURATION */
|
||||
SFR( P1MDOUT, 0xA5 ) ; /* PORT 1 OUTPUT MODE CONFIGURATION */
|
||||
SFR( P2MDOUT, 0xA6 ) ; /* PORT 2 OUTPUT MODE CONFIGURATION */
|
||||
SFR( IE, 0xA8 ) ; /* INTERRUPT ENABLE */
|
||||
SFR( CLKSEL, 0xA9 ) ; /* SYSTEM CLOCK SELECT */
|
||||
SFR( EMI0CN, 0xAA ) ; /* EXTERNAL MEMORY INTERFACE CONTROL */
|
||||
SFR( _XPAGE, 0xAA ) ; /* XDATA/PDATA PAGE */
|
||||
SFR( OSCXCN, 0xB1 ) ; /* EXTERNAL OSCILLATOR CONTROL */
|
||||
SFR( OSCICN, 0xB2 ) ; /* INTERNAL OSCILLATOR CONTROL */
|
||||
SFR( OSCICL, 0xB3 ) ; /* INTERNAL OSCILLATOR CALIBRATION */
|
||||
SFR( FLSCL, 0xB6 ) ; /* FLASH MEMORY TIMING PRESCALER */
|
||||
SFR( FLKEY, 0xB7 ) ; /* FLASH ACESS LIMIT */
|
||||
SFR( IP, 0xB8 ) ; /* INTERRUPT PRIORITY */
|
||||
SFR( IDA0CN, 0xB9 ) ; /* CURRENT MODE DAC 0 - CONTROL */
|
||||
SFR( AMX0N, 0xBA ) ; /* ADC 0 MUX NEGATIVE CHANNEL SELECTION */
|
||||
SFR( AMX0P, 0xBB ) ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */
|
||||
SFR( ADC0CF, 0xBC ) ; /* ADC 0 CONFIGURATION */
|
||||
SFR( ADC0L, 0xBD ) ; /* ADC 0 DATA WORD LSB */
|
||||
SFR( ADC0H, 0xBE ) ; /* ADC 0 DATA WORD MSB */
|
||||
SFR( SMB0CN, 0xC0 ) ; /* SMBUS CONTROL */
|
||||
SFR( SMB0CF, 0xC1 ) ; /* SMBUS CONFIGURATION */
|
||||
SFR( SMB0DAT, 0xC2 ) ; /* SMBUS DATA */
|
||||
SFR( ADC0GTL, 0xC3 ) ; /* ADC 0 GREATER-THAN LOW BYTE */
|
||||
SFR( ADC0GTH, 0xC4 ) ; /* ADC 0 GREATER-THAN HIGH BYTE */
|
||||
SFR( ADC0LTL, 0xC5 ) ; /* ADC 0 LESS-THAN LOW BYTE */
|
||||
SFR( ADC0LTH, 0xC6 ) ; /* ADC 0 LESS-THAN HIGH BYTE */
|
||||
SFR( T2CON, 0xC8 ) ; /* TIMER 2 CONTROL */
|
||||
SFR( TMR2CN, 0xC8 ) ; /* TIMER 2 CONTROL */
|
||||
SFR( RCAP2L, 0xCA ) ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
|
||||
SFR( TMR2RLL, 0xCA ) ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
|
||||
SFR( RCAP2H, 0xCB ) ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
|
||||
SFR( TMR2RLH, 0xCB ) ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
|
||||
SFR( TL2, 0xCC ) ; /* TIMER 2 - LOW BYTE */
|
||||
SFR( TMR2L, 0xCC ) ; /* TIMER 2 - LOW BYTE */
|
||||
SFR( TH2, 0xCD ) ; /* TIMER 2 - HIGH BYTE */
|
||||
SFR( TMR2H, 0xCD ) ; /* TIMER 2 - HIGH BYTE */
|
||||
SFR( PSW, 0xD0 ) ; /* PROGRAM STATUS WORD */
|
||||
SFR( REF0CN, 0xD1 ) ; /* VOLTAGE REFERENCE 0 CONTROL */
|
||||
SFR( P0SKIP, 0xD4 ) ; /* PORT 0 SKIP */
|
||||
SFR( P1SKIP, 0xD5 ) ; /* PORT 1 SKIP */
|
||||
SFR( P2SKIP, 0xD6 ) ; /* PORT 2 SKIP */
|
||||
SFR( SMB0ADR, 0xD7 ) ; /* SMBUS SLAVE ADDRESS */
|
||||
SFR( PCA0CN, 0xD8 ) ; /* PCA CONTROL */
|
||||
SFR( PCA0MD, 0xD9 ) ; /* PCA MODE */
|
||||
SFR( PCA0CPM0, 0xDA ) ; /* PCA MODULE 0 MODE REGISTER */
|
||||
SFR( PCA0CPM1, 0xDB ) ; /* PCA MODULE 1 MODE REGISTER */
|
||||
SFR( PCA0CPM2, 0xDC ) ; /* PCA MODULE 2 MODE REGISTER */
|
||||
SFR( ACC, 0xE0 ) ; /* ACCUMULATOR */
|
||||
SFR( XBR0, 0xE1 ) ; /* PORT MUX CONFIGURATION REGISTER 0 */
|
||||
SFR( XBR1, 0xE2 ) ; /* PORT MUX CONFIGURATION REGISTER 1 */
|
||||
SFR( OSCLCN, 0xE3 ) ; /* LOW-FREQUENCY OSCILLATOR CONTROL */
|
||||
SFR( IT01CF, 0xE4 ) ; /* INT0/INT1 CONFIGURATION REGISTER */
|
||||
SFR( INT01CF, 0xE4 ) ; /* INT0/INT1 CONFIGURATION REGISTER */
|
||||
SFR( EIE1, 0xE6 ) ; /* EXTERNAL INTERRUPT ENABLE 1 */
|
||||
SFR( SMB0ADM, 0xE7 ) ; /* SMBUS SLAVE ADDRESS MASK */
|
||||
SFR( ADC0CN, 0xE8 ) ; /* ADC 0 CONTROL */
|
||||
SFR( PCA0CPL1, 0xE9 ) ; /* PCA CAPTURE 1 LOW */
|
||||
SFR( PCA0CPH1, 0xEA ) ; /* PCA CAPTURE 1 HIGH */
|
||||
SFR( PCA0CPL2, 0xEB ) ; /* PCA CAPTURE 2 LOW */
|
||||
SFR( PCA0CPH2, 0xEC ) ; /* PCA CAPTURE 2 HIGH */
|
||||
SFR( P1MAT, 0xED ) ; /* PORT 1 MATCH REGISTER */
|
||||
SFR( P1MASK, 0xEE ) ; /* PORT 1 MASK REGISTER */
|
||||
SFR( RSTSRC, 0xEF ) ; /* RESET SOURCE */
|
||||
SFR( B, 0xF0 ) ; /* B REGISTER */
|
||||
SFR( P0MODE, 0xF1 ) ; /* PORT 0 INPUT MODE CONFIGURATION */
|
||||
SFR( P0MDIN, 0xF1 ) ; /* PORT 0 INPUT MODE CONFIGURATION */
|
||||
SFR( P1MODE, 0xF2 ) ; /* PORT 1 INPUT MODE CONFIGURATION */
|
||||
SFR( P1MDIN, 0xF2 ) ; /* PORT 1 INPUT MODE CONFIGURATION */
|
||||
SFR( P2MDIN, 0xF3 ) ; /* PORT 2 INPUT MODE */
|
||||
SFR( EIP1, 0xF6 ) ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
|
||||
SFR( PCA0PWM, 0xF7 ) ; /* PCA PWM CONFIGURATION */
|
||||
SFR( SPI0CN, 0xF8 ) ; /* SPI0 CONTROL */
|
||||
SFR( PCA0L, 0xF9 ) ; /* PCA COUNTER LOW */
|
||||
SFR( PCA0H, 0xFA ) ; /* PCA COUNTER HIGH */
|
||||
SFR( PCA0CPL0, 0xFB ) ; /* PCA CAPTURE 0 LOW */
|
||||
SFR( PCA0CPH0, 0xFC ) ; /* PCA CAPTURE 0 HIGH */
|
||||
SFR( P0MAT, 0xFD ) ; /* PORT 0 MATCH REGISTER */
|
||||
SFR( P0MASK, 0xFE ) ; /* PORT 0 MASK REGISTER */
|
||||
SFR( VDM0CN, 0xFF ) ; /* VDD MONITOR CONTROL */
|
||||
|
||||
|
||||
/* WORD/DWORD Registers */
|
||||
|
||||
SFR16E( TMR0, 0x8C8A ) ; /* TIMER 0 COUNTER */
|
||||
SFR16E( TMR1, 0x8D8B ) ; /* TIMER 1 COUNTER */
|
||||
SFR16E( TMR2, 0xCDCC ) ; /* TIMER 2 COUNTER */
|
||||
SFR16E( RCAP2, 0xCBCA ) ; /* TIMER 2 CAPTURE REGISTER WORD */
|
||||
SFR16E( TMR2RL, 0xCBCA ) ; /* TIMER 2 CAPTURE REGISTER WORD */
|
||||
SFR16E( TMR3, 0x9594 ) ; /* TIMER 3 COUNTER */
|
||||
SFR16E( TMR3RL, 0x9392 ) ; /* TIMER 3 CAPTURE REGISTER WORD */
|
||||
SFR16E( IDA0, 0x9796 ) ; /* CURRENT MODE DAC 0 DATA WORD */
|
||||
SFR16E( ADC0, 0xBEBD ) ; /* ADC 0 DATA WORD */
|
||||
SFR16E( ADC0GT, 0xC4C3 ) ; /* ADC 0 GREATER-THAN REGISTER WORD */
|
||||
SFR16E( ADC0LT, 0xC6C5 ) ; /* ADC 0 LESS-THAN REGISTER WORD */
|
||||
SFR16E( PCA0, 0xFAF9 ) ; /* PCA COUNTER */
|
||||
SFR16E( PCA0CP0, 0xFCFB ) ; /* PCA CAPTURE 0 WORD */
|
||||
SFR16E( PCA0CP1, 0xEAE9 ) ; /* PCA CAPTURE 1 WORD */
|
||||
SFR16E( PCA0CP2, 0xECEB ) ; /* PCA CAPTURE 2 WORD */
|
||||
|
||||
|
||||
/* BIT Registers */
|
||||
|
||||
/* P0 0x80 */
|
||||
SBIT( P0_0, 0x80, 0 ) ;
|
||||
SBIT( P0_1, 0x80, 1 ) ;
|
||||
SBIT( P0_2, 0x80, 2 ) ;
|
||||
SBIT( P0_3, 0x80, 3 ) ;
|
||||
SBIT( P0_4, 0x80, 4 ) ;
|
||||
SBIT( P0_5, 0x80, 5 ) ;
|
||||
SBIT( P0_6, 0x80, 6 ) ;
|
||||
SBIT( P0_7, 0x80, 7 ) ;
|
||||
|
||||
/* TCON 0x88 */
|
||||
SBIT( IT0, 0x88, 0 ) ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
|
||||
SBIT( IE0, 0x88, 1 ) ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
|
||||
SBIT( IT1, 0x88, 2 ) ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
|
||||
SBIT( IE1, 0x88, 3 ) ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
|
||||
SBIT( TR0, 0x88, 4 ) ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
|
||||
SBIT( TF0, 0x88, 5 ) ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
|
||||
SBIT( TR1, 0x88, 6 ) ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
|
||||
SBIT( TF1, 0x88, 7 ) ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
|
||||
|
||||
/* P1 0x90 */
|
||||
SBIT( P1_0, 0x90, 0 ) ;
|
||||
SBIT( P1_1, 0x90, 1 ) ;
|
||||
SBIT( P1_2, 0x90, 2 ) ;
|
||||
SBIT( P1_3, 0x90, 3 ) ;
|
||||
SBIT( P1_4, 0x90, 4 ) ;
|
||||
SBIT( P1_5, 0x90, 5 ) ;
|
||||
SBIT( P1_6, 0x90, 6 ) ;
|
||||
SBIT( P1_7, 0x90, 7 ) ;
|
||||
|
||||
/* SCON 0x98 */
|
||||
SBIT( RI, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
|
||||
SBIT( RI0, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
|
||||
SBIT( TI, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
|
||||
SBIT( TI0, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
|
||||
SBIT( RB8, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */
|
||||
SBIT( RB80, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */
|
||||
SBIT( TB8, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */
|
||||
SBIT( TB80, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */
|
||||
SBIT( REN, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */
|
||||
SBIT( REN0, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */
|
||||
SBIT( SM2, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
|
||||
SBIT( MCE0, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
|
||||
SBIT( SM0, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
|
||||
SBIT( S0MODE, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
|
||||
|
||||
/* P2 0xA0 */
|
||||
SBIT( P2_0, 0xA0, 0 ) ;
|
||||
SBIT( P2_1, 0xA0, 1 ) ;
|
||||
SBIT( P2_2, 0xA0, 2 ) ;
|
||||
SBIT( P2_3, 0xA0, 3 ) ;
|
||||
SBIT( P2_4, 0xA0, 4 ) ;
|
||||
SBIT( P2_5, 0xA0, 5 ) ;
|
||||
SBIT( P2_6, 0xA0, 6 ) ;
|
||||
SBIT( P2_7, 0xA0, 7 ) ;
|
||||
|
||||
/* IE 0xA8 */
|
||||
SBIT( EX0, 0xA8, 0 ) ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
|
||||
SBIT( ET0, 0xA8, 1 ) ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
|
||||
SBIT( EX1, 0xA8, 2 ) ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
|
||||
SBIT( ET1, 0xA8, 3 ) ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
|
||||
SBIT( ES, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
|
||||
SBIT( ES0, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
|
||||
SBIT( ET2, 0xA8, 5 ) ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
|
||||
SBIT( ESPI0, 0xA8, 6 ) ; /* IE.6 - SPI0 INTERRUPT ENABLE */
|
||||
SBIT( EA, 0xA8, 7 ) ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
|
||||
|
||||
/* IP 0xB8 */
|
||||
SBIT( PX0, 0xB8, 0 ) ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
|
||||
SBIT( PT0, 0xB8, 1 ) ; /* IP.1 - TIMER 0 PRIORITY */
|
||||
SBIT( PX1, 0xB8, 2 ) ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
|
||||
SBIT( PT1, 0xB8, 3 ) ; /* IP.3 - TIMER 1 PRIORITY */
|
||||
SBIT( PS, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */
|
||||
SBIT( PS0, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */
|
||||
SBIT( PT2, 0xB8, 5 ) ; /* IP.5 - TIMER 2 PRIORITY */
|
||||
SBIT( PSPI0, 0xB8, 6 ) ; /* IP.6 - SPI0 PRIORITY */
|
||||
|
||||
/* SMB0CN 0xC0 */
|
||||
SBIT( SI, 0xC0, 0 ) ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
|
||||
SBIT( ACK, 0xC0, 1 ) ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
|
||||
SBIT( ARBLOST, 0xC0, 2 ) ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
|
||||
SBIT( ACKRQ, 0xC0, 3 ) ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
|
||||
SBIT( STO, 0xC0, 4 ) ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
|
||||
SBIT( STA, 0xC0, 5 ) ; /* SMB0CN.5 - SMBUS 0 START FLAG */
|
||||
SBIT( TXMODE, 0xC0, 6 ) ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
|
||||
SBIT( MASTER, 0xC0, 7 ) ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
|
||||
|
||||
/* TMR2CN 0xC8 */
|
||||
SBIT( T2XCLK, 0xC8, 0 ) ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
|
||||
SBIT( TR2, 0xC8, 2 ) ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
|
||||
SBIT( T2SPLIT, 0xC8, 3 ) ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
|
||||
SBIT( TF2CEN, 0xC8, 4 ) ; /* TMR2CN.4 - TIMER 2 LOW-FREQ OSC CAPTURE ENABLE*/
|
||||
SBIT( TF2LEN, 0xC8, 5 ) ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
|
||||
SBIT( TF2L, 0xC8, 6 ) ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
|
||||
SBIT( TF2, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
|
||||
SBIT( TF2H, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
|
||||
|
||||
/* PSW 0xD0 */
|
||||
SBIT( PARITY, 0xD0, 0 ) ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
|
||||
SBIT( F1, 0xD0, 1 ) ; /* PSW.1 - FLAG 1 */
|
||||
SBIT( OV, 0xD0, 2 ) ; /* PSW.2 - OVERFLOW FLAG */
|
||||
SBIT( RS0, 0xD0, 3 ) ; /* PSW.3 - REGISTER BANK SELECT 0 */
|
||||
SBIT( RS1, 0xD0, 4 ) ; /* PSW.4 - REGISTER BANK SELECT 1 */
|
||||
SBIT( F0, 0xD0, 5 ) ; /* PSW.5 - FLAG 0 */
|
||||
SBIT( AC, 0xD0, 6 ) ; /* PSW.6 - AUXILIARY CARRY FLAG */
|
||||
SBIT( CY, 0xD0, 7 ) ; /* PSW.7 - CARRY FLAG */
|
||||
|
||||
/* PCA0CN 0xD8 */
|
||||
SBIT( CCF0, 0xD8, 0 ) ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
|
||||
SBIT( CCF1, 0xD8, 1 ) ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
|
||||
SBIT( CCF2, 0xD8, 2 ) ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
|
||||
SBIT( CR, 0xD8, 6 ) ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
|
||||
SBIT( CF, 0xD8, 7 ) ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
|
||||
|
||||
/* ADC0CN 0xE8 */
|
||||
SBIT( AD0CM0, 0xE8, 0 ) ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
|
||||
SBIT( AD0CM1, 0xE8, 1 ) ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
|
||||
SBIT( AD0CM2, 0xE8, 2 ) ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
|
||||
SBIT( AD0WINT, 0xE8, 3 ) ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
|
||||
SBIT( AD0BUSY, 0xE8, 4 ) ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
|
||||
SBIT( AD0INT, 0xE8, 5 ) ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
|
||||
SBIT( AD0TM, 0xE8, 6 ) ; /* ADC0CN.6 - ADC 0 TRACK MODE */
|
||||
SBIT( AD0EN, 0xE8, 7 ) ; /* ADC0CN.7 - ADC 0 ENABLE */
|
||||
|
||||
/* SPI0CN 0xF8 */
|
||||
SBIT( SPIEN, 0xF8, 0 ) ; /* SPI0CN.0 - SPI0 ENABLE */
|
||||
SBIT( TXBMT, 0xF8, 1 ) ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
|
||||
SBIT( NSSMD0, 0xF8, 2 ) ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
|
||||
SBIT( NSSMD1, 0xF8, 3 ) ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
|
||||
SBIT( RXOVRN, 0xF8, 4 ) ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
|
||||
SBIT( MODF, 0xF8, 5 ) ; /* SPI0CN.5 - MODE FAULT FLAG */
|
||||
SBIT( WCOL, 0xF8, 6 ) ; /* SPI0CN.6 - WRITE COLLISION FLAG */
|
||||
SBIT( SPIF, 0xF8, 7 ) ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
|
||||
|
||||
|
||||
/* Predefined SFR Bit Masks */
|
||||
|
||||
#define PCON_IDLE 0x01 /* PCON */
|
||||
#define PCON_STOP 0x02 /* PCON */
|
||||
#define T1M 0x08 /* CKCON */
|
||||
#define PSWE 0x01 /* PSCTL */
|
||||
#define PSEE 0x02 /* PSCTL */
|
||||
#define ECP0 0x20 /* EIE1 */
|
||||
#define PORSF 0x02 /* RSTSRC */
|
||||
#define SWRSF 0x10 /* RSTSRC */
|
||||
#define ECCF 0x01 /* PCA0CPMn */
|
||||
#define PWM 0x02 /* PCA0CPMn */
|
||||
#define TOG 0x04 /* PCA0CPMn */
|
||||
#define MAT 0x08 /* PCA0CPMn */
|
||||
#define CAPN 0x10 /* PCA0CPMn */
|
||||
#define CAPP 0x20 /* PCA0CPMn */
|
||||
#define ECOM 0x40 /* PCA0CPMn */
|
||||
#define PWM16 0x80 /* PCA0CPMn */
|
||||
#define CP0E 0x10 /* XBR0 */
|
||||
#define CP0OEN 0x10 /* XBR0 */
|
||||
#define CP0AE 0x20 /* XBR0 */
|
||||
#define CP0AOEN 0x20 /* XBR0 */
|
||||
|
||||
/* Interrupts */
|
||||
|
||||
#define INT_EXT0 0 /* External Interrupt 0 */
|
||||
#define INT_TIMER0 1 /* Timer0 Overflow */
|
||||
#define INT_EXT1 2 /* External Interrupt 1 */
|
||||
#define INT_TIMER1 3 /* Timer1 Overflow */
|
||||
#define INT_UART0 4 /* Serial Port 0 */
|
||||
#define INT_TIMER2 5 /* Timer2 Overflow */
|
||||
#define INT_SPI0 6 /* Serial Peripheral Interface 0 */
|
||||
#define INT_SMBUS0 7 /* SMBus0 Interface */
|
||||
#define INT_PMAT 8 /* Port match */
|
||||
#define INT_ADC0_WINDOW 9 /* ADC0 Window Comparison */
|
||||
#define INT_ADC0_EOC 10 /* ADC0 End Of Conversion */
|
||||
#define INT_PCA0 11 /* PCA0 Peripheral */
|
||||
#define INT_COMPARATOR0 12 /* Comparator0 */
|
||||
/* 13 Reserved */
|
||||
#define INT_TIMER3 14 /* Timer3 Overflow */
|
||||
|
||||
#endif
|
||||
368
lib/mcs51/C8051F340.h
Normal file
368
lib/mcs51/C8051F340.h
Normal file
@@ -0,0 +1,368 @@
|
||||
/*-------------------------------------------------------------------------
|
||||
C8051F340.h - Register Declarations for the Cygnal/SiLabs C8051F34x
|
||||
Processor Range
|
||||
|
||||
Copyright (C) 2006, Maarten Brock, sourceforge.brock@dse.nl
|
||||
|
||||
This library is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the
|
||||
Free Software Foundation; either version 2, or (at your option) any
|
||||
later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this library; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
|
||||
MA 02110-1301, USA.
|
||||
|
||||
As a special exception, if you link this library with other files,
|
||||
some of which are compiled with SDCC, to produce an executable,
|
||||
this library does not by itself cause the resulting executable to
|
||||
be covered by the GNU General Public License. This exception does
|
||||
not however invalidate any other reasons why the executable file
|
||||
might be covered by the GNU General Public License.
|
||||
-------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef C8051F340_H
|
||||
#define C8051F340_H
|
||||
|
||||
|
||||
/* BYTE Registers */
|
||||
__sfr __at (0x80) P0 ; /* PORT 0 */
|
||||
__sfr __at (0x81) SP ; /* STACK POINTER */
|
||||
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
|
||||
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
|
||||
__sfr __at (0x84) EMI0TC ; /* EXTERNAL MEMORY INTERFACE TIMING */
|
||||
__sfr __at (0x85) EMI0CF ; /* EXTERNAL MEMORY INTERFACE CONFIGURATION */
|
||||
__sfr __at (0x86) OSCLCN ; /* LOW-FREQUENCY OSCILLATOR CONTROL */
|
||||
__sfr __at (0x87) PCON ; /* POWER CONTROL */
|
||||
__sfr __at (0x88) TCON ; /* TIMER CONTROL */
|
||||
__sfr __at (0x89) TMOD ; /* TIMER MODE */
|
||||
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
|
||||
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
|
||||
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
|
||||
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
|
||||
__sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
|
||||
__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
|
||||
__sfr __at (0x90) P1 ; /* PORT 1 */
|
||||
__sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */
|
||||
__sfr __at (0x92) TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at (0x93) TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */
|
||||
__sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */
|
||||
__sfr __at (0x96) USB0ADR ; /* USB0 INDIRECT ADDRESS REGISTER */
|
||||
__sfr __at (0x97) USB0DAT ; /* USB0 DATA REGISTER */
|
||||
__sfr __at (0x98) SCON ; /* SERIAL PORT CONTROL */
|
||||
__sfr __at (0x98) SCON0 ; /* SERIAL PORT CONTROL */
|
||||
__sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
|
||||
__sfr __at (0x99) SBUF0 ; /* SERIAL PORT BUFFER */
|
||||
__sfr __at (0x9A) CPT1CN ; /* COMPARATOR 1 CONTROL */
|
||||
__sfr __at (0x9B) CPT0CN ; /* COMPARATOR 0 CONTROL */
|
||||
__sfr __at (0x9C) CPT1MD ; /* COMPARATOR 1 MODE SELECTION */
|
||||
__sfr __at (0x9D) CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
|
||||
__sfr __at (0x9E) CPT1MX ; /* COMPARATOR 1 MUX SELECTION */
|
||||
__sfr __at (0x9F) CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
|
||||
__sfr __at (0xA0) P2 ; /* PORT 2 */
|
||||
__sfr __at (0xA1) SPI0CFG ; /* SPI0 CONFIGURATION */
|
||||
__sfr __at (0xA2) SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */
|
||||
__sfr __at (0xA3) SPI0DAT ; /* SPI0 DATA */
|
||||
__sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA5) P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA7) P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
|
||||
__sfr __at (0xA9) CLKSEL ; /* SYSTEM CLOCK SELECT */
|
||||
__sfr __at (0xAA) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
|
||||
__sfr __at (0xAA) _XPAGE ; /* XDATA/PDATA PAGE */
|
||||
__sfr __at (0xAC) SBCON1 ; /* UART 1 BAUDRATE GENERATOR CONTROL */
|
||||
__sfr __at (0xAE) P4MDOUT ; /* PORT 4 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xAF) PFE0CN ; /* PREFETCH ENGINE CONTROL */
|
||||
__sfr __at (0xB0) P3 ; /* PORT 3 */
|
||||
__sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at (0xB3) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
|
||||
__sfr __at (0xB4) SBRLL1 ; /* UART 1 BAUDRATE GENERATOR - LOW BYTE */
|
||||
__sfr __at (0xB5) SBRLH1 ; /* UART 1 BAUDRATE GENERATOR - HIGH BYTE */
|
||||
__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
|
||||
__sfr __at (0xB7) FLKEY ; /* FLASH ACESS LIMIT */
|
||||
__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
|
||||
__sfr __at (0xB9) CLKMUL ; /* CLOCK MULTIPLIER CONTROL REGISTER */
|
||||
__sfr __at (0xBA) AMX0N ; /* ADC 0 MUX NEGATIVE CHANNEL SELECTION */
|
||||
__sfr __at (0xBB) AMX0P ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */
|
||||
__sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */
|
||||
__sfr __at (0xBD) ADC0L ; /* ADC 0 DATA WORD LSB */
|
||||
__sfr __at (0xBE) ADC0H ; /* ADC 0 DATA WORD MSB */
|
||||
__sfr __at (0xC0) SMB0CN ; /* SMBUS CONTROL */
|
||||
__sfr __at (0xC1) SMB0CF ; /* SMBUS CONFIGURATION */
|
||||
__sfr __at (0xC2) SMB0DAT ; /* SMBUS DATA */
|
||||
__sfr __at (0xC3) ADC0GTL ; /* ADC 0 GREATER-THAN LOW BYTE */
|
||||
__sfr __at (0xC4) ADC0GTH ; /* ADC 0 GREATER-THAN HIGH BYTE */
|
||||
__sfr __at (0xC5) ADC0LTL ; /* ADC 0 LESS-THAN LOW BYTE */
|
||||
__sfr __at (0xC6) ADC0LTH ; /* ADC 0 LESS-THAN HIGH BYTE */
|
||||
__sfr __at (0xC7) P4 ; /* PORT 4 */
|
||||
__sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
|
||||
__sfr __at (0xC8) TMR2CN ; /* TIMER 2 CONTROL */
|
||||
__sfr __at (0xC9) REG0CN ; /* VOLTAGE REGULATOR CONTROL */
|
||||
__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at (0xCA) TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xCB) TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
|
||||
__sfr __at (0xCC) TMR2L ; /* TIMER 2 - LOW BYTE */
|
||||
__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
|
||||
__sfr __at (0xCD) TMR2H ; /* TIMER 2 - HIGH BYTE */
|
||||
__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
|
||||
__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
|
||||
__sfr __at (0xD2) SCON1 ; /* UART 1 CONTROL */
|
||||
__sfr __at (0xD3) SBUF1 ; /* UART 1 DATA BUFFER */
|
||||
__sfr __at (0xD4) P0SKIP ; /* PORT 0 SKIP */
|
||||
__sfr __at (0xD5) P1SKIP ; /* PORT 1 SKIP */
|
||||
__sfr __at (0xD6) P2SKIP ; /* PORT 2 SKIP */
|
||||
__sfr __at (0xD7) USB0XCN ; /* USB0 TRANSCEIVER CONTROL */
|
||||
__sfr __at (0xD8) PCA0CN ; /* PCA CONTROL */
|
||||
__sfr __at (0xD9) PCA0MD ; /* PCA MODE */
|
||||
__sfr __at (0xDA) PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
|
||||
__sfr __at (0xDB) PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
|
||||
__sfr __at (0xDC) PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
|
||||
__sfr __at (0xDD) PCA0CPM3 ; /* PCA MODULE 3 MODE REGISTER */
|
||||
__sfr __at (0xDE) PCA0CPM4 ; /* PCA MODULE 4 MODE REGISTER */
|
||||
__sfr __at (0xDF) P3SKIP ; /* PORT 3 SKIP */
|
||||
__sfr __at (0xE0) ACC ; /* ACCUMULATOR */
|
||||
__sfr __at (0xE1) XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
|
||||
__sfr __at (0xE2) XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
|
||||
__sfr __at (0xE3) XBR2 ; /* PORT MUX CONFIGURATION REGISTER 2 */
|
||||
__sfr __at (0xE4) IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
|
||||
__sfr __at (0xE4) INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
|
||||
__sfr __at (0xE5) SMOD1 ; /* UART 1 MODE */
|
||||
__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
|
||||
__sfr __at (0xE7) EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
|
||||
__sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */
|
||||
__sfr __at (0xE9) PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
|
||||
__sfr __at (0xEA) PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
|
||||
__sfr __at (0xEB) PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
|
||||
__sfr __at (0xEC) PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
|
||||
__sfr __at (0xED) PCA0CPL3 ; /* PCA CAPTURE 3 LOW */
|
||||
__sfr __at (0xEE) PCA0CPH3 ; /* PCA CAPTURE 3 HIGH */
|
||||
__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
|
||||
__sfr __at (0xF0) B ; /* B REGISTER */
|
||||
__sfr __at (0xF1) P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF1) P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF2) P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF2) P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF3) P2MODE ; /* PORT 2 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF3) P2MDIN ; /* PORT 2 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF4) P3MODE ; /* PORT 3 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF4) P3MDIN ; /* PORT 3 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF5) P4MDIN ; /* PORT 4 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
|
||||
__sfr __at (0xF7) EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
|
||||
__sfr __at (0xF8) SPI0CN ; /* SPI0 CONTROL */
|
||||
__sfr __at (0xF9) PCA0L ; /* PCA COUNTER LOW */
|
||||
__sfr __at (0xFA) PCA0H ; /* PCA COUNTER HIGH */
|
||||
__sfr __at (0xFB) PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
|
||||
__sfr __at (0xFC) PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
|
||||
__sfr __at (0xFD) PCA0CPL4 ; /* PCA CAPTURE 4 LOW */
|
||||
__sfr __at (0xFE) PCA0CPH4 ; /* PCA CAPTURE 4 HIGH */
|
||||
__sfr __at (0xFF) VDM0CN ; /* VDD MONITOR CONTROL */
|
||||
|
||||
|
||||
/* WORD/DWORD Registers */
|
||||
|
||||
__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
|
||||
__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
|
||||
__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
|
||||
__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
|
||||
__sfr16 __at (0xCBCA) TMR2RL ; /* TIMER 2 CAPTURE REGISTER WORD */
|
||||
__sfr16 __at (0x9594) TMR3 ; /* TIMER 3 COUNTER */
|
||||
__sfr16 __at (0x9392) TMR3RL ; /* TIMER 3 CAPTURE REGISTER WORD */
|
||||
__sfr16 __at (0xB5B4) SBRL1 ; /* UART 1 BAUDRATE GENERATOR WORD */
|
||||
__sfr16 __at (0xBEBD) ADC0 ; /* ADC 0 DATA WORD */
|
||||
__sfr16 __at (0xC4C3) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */
|
||||
__sfr16 __at (0xC6C5) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */
|
||||
__sfr16 __at (0xFAF9) PCA0 ; /* PCA COUNTER */
|
||||
__sfr16 __at (0xFCFB) PCA0CP0 ; /* PCA CAPTURE 0 WORD */
|
||||
__sfr16 __at (0xEAE9) PCA0CP1 ; /* PCA CAPTURE 1 WORD */
|
||||
__sfr16 __at (0xECEB) PCA0CP2 ; /* PCA CAPTURE 2 WORD */
|
||||
__sfr16 __at (0xEEED) PCA0CP3 ; /* PCA CAPTURE 3 WORD */
|
||||
__sfr16 __at (0xFEFD) PCA0CP4 ; /* PCA CAPTURE 4 WORD */
|
||||
|
||||
|
||||
/* BIT Registers */
|
||||
|
||||
/* P0 0x80 */
|
||||
__sbit __at (0x80) P0_0 ;
|
||||
__sbit __at (0x81) P0_1 ;
|
||||
__sbit __at (0x82) P0_2 ;
|
||||
__sbit __at (0x83) P0_3 ;
|
||||
__sbit __at (0x84) P0_4 ;
|
||||
__sbit __at (0x85) P0_5 ;
|
||||
__sbit __at (0x86) P0_6 ;
|
||||
__sbit __at (0x87) P0_7 ;
|
||||
|
||||
/* TCON 0x88 */
|
||||
__sbit __at (0x88) IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
|
||||
__sbit __at (0x89) IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
|
||||
__sbit __at (0x8A) IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
|
||||
__sbit __at (0x8B) IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
|
||||
__sbit __at (0x8C) TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
|
||||
__sbit __at (0x8D) TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
|
||||
__sbit __at (0x8E) TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
|
||||
__sbit __at (0x8F) TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
|
||||
|
||||
/* P1 0x90 */
|
||||
__sbit __at (0x90) P1_0 ;
|
||||
__sbit __at (0x91) P1_1 ;
|
||||
__sbit __at (0x92) P1_2 ;
|
||||
__sbit __at (0x93) P1_3 ;
|
||||
__sbit __at (0x94) P1_4 ;
|
||||
__sbit __at (0x95) P1_5 ;
|
||||
__sbit __at (0x96) P1_6 ;
|
||||
__sbit __at (0x97) P1_7 ;
|
||||
|
||||
/* SCON 0x98 */
|
||||
__sbit __at (0x98) RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
|
||||
__sbit __at (0x98) RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
|
||||
__sbit __at (0x99) TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
|
||||
__sbit __at (0x99) TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
|
||||
__sbit __at (0x9A) RB8 ; /* SCON.2 - RECEIVE BIT 8 */
|
||||
__sbit __at (0x9A) RB80 ; /* SCON.2 - RECEIVE BIT 8 */
|
||||
__sbit __at (0x9B) TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
|
||||
__sbit __at (0x9B) TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
|
||||
__sbit __at (0x9C) REN ; /* SCON.4 - RECEIVE ENABLE */
|
||||
__sbit __at (0x9C) REN0 ; /* SCON.4 - RECEIVE ENABLE */
|
||||
__sbit __at (0x9D) SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
|
||||
__sbit __at (0x9D) MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
|
||||
__sbit __at (0x9F) SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
|
||||
__sbit __at (0x9F) S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
|
||||
|
||||
/* P2 0xA0 */
|
||||
__sbit __at (0xA0) P2_0 ;
|
||||
__sbit __at (0xA1) P2_1 ;
|
||||
__sbit __at (0xA2) P2_2 ;
|
||||
__sbit __at (0xA3) P2_3 ;
|
||||
__sbit __at (0xA4) P2_4 ;
|
||||
__sbit __at (0xA5) P2_5 ;
|
||||
__sbit __at (0xA6) P2_6 ;
|
||||
__sbit __at (0xA7) P2_7 ;
|
||||
|
||||
/* IE 0xA8 */
|
||||
__sbit __at (0xA8) EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
|
||||
__sbit __at (0xA9) ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAA) EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
|
||||
__sbit __at (0xAB) ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAC) ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
|
||||
__sbit __at (0xAC) ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
|
||||
__sbit __at (0xAD) ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAE) ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAF) EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
|
||||
|
||||
/* P3 0xB0 */
|
||||
__sbit __at (0xB0) P3_0 ;
|
||||
__sbit __at (0xB1) P3_1 ;
|
||||
__sbit __at (0xB2) P3_2 ;
|
||||
__sbit __at (0xB3) P3_3 ;
|
||||
__sbit __at (0xB4) P3_4 ;
|
||||
__sbit __at (0xB5) P3_5 ;
|
||||
__sbit __at (0xB6) P3_6 ;
|
||||
__sbit __at (0xB7) P3_7 ;
|
||||
|
||||
/* IP 0xB8 */
|
||||
__sbit __at (0xB8) PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
|
||||
__sbit __at (0xB9) PT0 ; /* IP.1 - TIMER 0 PRIORITY */
|
||||
__sbit __at (0xBA) PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
|
||||
__sbit __at (0xBB) PT1 ; /* IP.3 - TIMER 1 PRIORITY */
|
||||
__sbit __at (0xBC) PS ; /* IP.4 - SERIAL PORT PRIORITY */
|
||||
__sbit __at (0xBC) PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
|
||||
__sbit __at (0xBD) PT2 ; /* IP.5 - TIMER 2 PRIORITY */
|
||||
__sbit __at (0xBE) PSPI0 ; /* IP.6 - SPI0 PRIORITY */
|
||||
|
||||
/* SMB0CN 0xC0 */
|
||||
__sbit __at (0xC0) SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
|
||||
__sbit __at (0xC1) ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
|
||||
__sbit __at (0xC2) ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
|
||||
__sbit __at (0xC3) ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
|
||||
__sbit __at (0xC4) STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
|
||||
__sbit __at (0xC5) STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
|
||||
__sbit __at (0xC6) TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
|
||||
__sbit __at (0xC7) MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
|
||||
|
||||
/* TMR2CN 0xC8 */
|
||||
__sbit __at (0xC8) T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
|
||||
__sbit __at (0xC9) T2CSS ; /* TMR2CN.1 - TIMER 2 CAPTURE SOURCE SELECT */
|
||||
__sbit __at (0xCA) TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
|
||||
__sbit __at (0xCB) T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
|
||||
__sbit __at (0xCC) T2CE ; /* TMR2CN.4 - TIMER 2 CAPTURE ENABLE */
|
||||
__sbit __at (0xCD) TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
|
||||
__sbit __at (0xCE) TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
|
||||
__sbit __at (0xCF) TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
|
||||
__sbit __at (0xCF) TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
|
||||
|
||||
/* PSW 0xD0 */
|
||||
__sbit __at (0xD0) PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
|
||||
__sbit __at (0xD1) F1 ; /* PSW.1 - FLAG 1 */
|
||||
__sbit __at (0xD2) OV ; /* PSW.2 - OVERFLOW FLAG */
|
||||
__sbit __at (0xD3) RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
|
||||
__sbit __at (0xD4) RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
|
||||
__sbit __at (0xD5) F0 ; /* PSW.5 - FLAG 0 */
|
||||
__sbit __at (0xD6) AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
|
||||
__sbit __at (0xD7) CY ; /* PSW.7 - CARRY FLAG */
|
||||
|
||||
/* PCA0CN 0xD8 */
|
||||
__sbit __at (0xD8) CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
|
||||
__sbit __at (0xD9) CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
|
||||
__sbit __at (0xDA) CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
|
||||
__sbit __at (0xDB) CCF3 ; /* PCA0CN.3 - PCA MODULE 3 CAPTURE/COMPARE FLAG */
|
||||
__sbit __at (0xDC) CCF4 ; /* PCA0CN.4 - PCA MODULE 4 CAPTURE/COMPARE FLAG */
|
||||
__sbit __at (0xDE) CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
|
||||
__sbit __at (0xDF) CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
|
||||
|
||||
/* ADC0CN 0xE8 */
|
||||
__sbit __at (0xE8) AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
|
||||
__sbit __at (0xE9) AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
|
||||
__sbit __at (0xEA) AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
|
||||
__sbit __at (0xEB) AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
|
||||
__sbit __at (0xEC) AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
|
||||
__sbit __at (0xED) AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
|
||||
__sbit __at (0xEE) AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */
|
||||
__sbit __at (0xEF) AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */
|
||||
|
||||
/* SPI0CN 0xF8 */
|
||||
__sbit __at (0xF8) SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */
|
||||
__sbit __at (0xF9) TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
|
||||
__sbit __at (0xFA) NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
|
||||
__sbit __at (0xFB) NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
|
||||
__sbit __at (0xFC) RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
|
||||
__sbit __at (0xFD) MODF ; /* SPI0CN.5 - MODE FAULT FLAG */
|
||||
__sbit __at (0xFE) WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */
|
||||
__sbit __at (0xFF) SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
|
||||
|
||||
|
||||
/* Predefined SFR Bit Masks */
|
||||
|
||||
#define PCON_IDLE 0x01 /* PCON */
|
||||
#define PCON_STOP 0x02 /* PCON */
|
||||
#define T1M 0x08 /* CKCON */
|
||||
#define PSWE 0x01 /* PSCTL */
|
||||
#define PSEE 0x02 /* PSCTL */
|
||||
#define ECP0 0x20 /* EIE1 */
|
||||
#define ECP1 0x40 /* EIE1 */
|
||||
#define PORSF 0x02 /* RSTSRC */
|
||||
#define SWRSF 0x10 /* RSTSRC */
|
||||
#define ECCF 0x01 /* PCA0CPMn */
|
||||
#define PWM 0x02 /* PCA0CPMn */
|
||||
#define TOG 0x04 /* PCA0CPMn */
|
||||
#define MAT 0x08 /* PCA0CPMn */
|
||||
#define CAPN 0x10 /* PCA0CPMn */
|
||||
#define CAPP 0x20 /* PCA0CPMn */
|
||||
#define ECOM 0x40 /* PCA0CPMn */
|
||||
#define PWM16 0x80 /* PCA0CPMn */
|
||||
#define CP0E 0x10 /* XBR0 */
|
||||
#define CP0AE 0x20 /* XBR0 */
|
||||
#define CP1E 0x40 /* XBR0 */
|
||||
#define CP1AE 0x80 /* XBR0 */
|
||||
|
||||
#endif
|
||||
337
lib/mcs51/C8051F350.h
Normal file
337
lib/mcs51/C8051F350.h
Normal file
@@ -0,0 +1,337 @@
|
||||
/*-------------------------------------------------------------------------
|
||||
C8051F350.h - Register Declarations for the SiLabs C8051F35x
|
||||
Processor Range
|
||||
|
||||
Copyright (C) 2004, Maarten Brock, sourceforge.brock@dse.nl
|
||||
|
||||
This library is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the
|
||||
Free Software Foundation; either version 2, or (at your option) any
|
||||
later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this library; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
|
||||
MA 02110-1301, USA.
|
||||
|
||||
As a special exception, if you link this library with other files,
|
||||
some of which are compiled with SDCC, to produce an executable,
|
||||
this library does not by itself cause the resulting executable to
|
||||
be covered by the GNU General Public License. This exception does
|
||||
not however invalidate any other reasons why the executable file
|
||||
might be covered by the GNU General Public License.
|
||||
-------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef C8051F350_H
|
||||
#define C8051F350_H
|
||||
|
||||
|
||||
/* BYTE Registers */
|
||||
|
||||
__sfr __at (0x80) P0 ; /* PORT 0 */
|
||||
__sfr __at (0x81) SP ; /* STACK POINTER */
|
||||
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
|
||||
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
|
||||
__sfr __at (0x87) PCON ; /* POWER CONTROL */
|
||||
__sfr __at (0x88) TCON ; /* TIMER CONTROL */
|
||||
__sfr __at (0x89) TMOD ; /* TIMER MODE */
|
||||
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
|
||||
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
|
||||
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
|
||||
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
|
||||
__sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
|
||||
__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
|
||||
__sfr __at (0x90) P1 ; /* PORT 1 */
|
||||
__sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */
|
||||
__sfr __at (0x92) TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at (0x93) TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */
|
||||
__sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */
|
||||
__sfr __at (0x96) IDA0 ; /* CURRENT MODE DAC 0 */
|
||||
__sfr __at (0x98) SCON ; /* SERIAL PORT CONTROL */
|
||||
__sfr __at (0x98) SCON0 ; /* SERIAL PORT CONTROL */
|
||||
__sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
|
||||
__sfr __at (0x99) SBUF0 ; /* SERIAL PORT BUFFER */
|
||||
__sfr __at (0x9A) ADC0DECL ; /* ADC DECIMATION LOW */
|
||||
__sfr __at (0x9B) ADC0DECH ; /* ADC DECIMATION HIGH */
|
||||
__sfr __at (0x9C) CPT0CN ; /* COMPARATOR 0 CONTROL */
|
||||
__sfr __at (0x9D) CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
|
||||
__sfr __at (0x9F) CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
|
||||
__sfr __at (0xA0) P2 ; /* PORT 2 */
|
||||
__sfr __at (0xA1) SPI0CFG ; /* SPI0 CONFIGURATION */
|
||||
__sfr __at (0xA2) SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */
|
||||
__sfr __at (0xA3) SPI0DAT ; /* SPI0 DATA */
|
||||
__sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA5) P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
|
||||
__sfr __at (0xA9) CLKSEL ; /* SYSTEM CLOCK SELECT */
|
||||
__sfr __at (0xAA) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
|
||||
__sfr __at (0xAA) _XPAGE ; /* XDATA/PDATA PAGE */
|
||||
__sfr __at (0xAB) ADC0CGL ; /* ADC 0 GAIN CALIBRATION LOW */
|
||||
__sfr __at (0xAC) ADC0CGM ; /* ADC 0 GAIN CALIBRATION MIDDLE */
|
||||
__sfr __at (0xAD) ADC0CGH ; /* ADC 0 GAIN CALIBRATION HIGH */
|
||||
__sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at (0xB3) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
|
||||
__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
|
||||
__sfr __at (0xB7) FLKEY ; /* FLASH ACESS LIMIT */
|
||||
__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
|
||||
__sfr __at (0xB9) IDA0CN ; /* CURRENT MODE DAC 0 - CONTROL */
|
||||
__sfr __at (0xBA) ADC0COL ; /* ADC 0 OFFSET CALIBRATION LOW */
|
||||
__sfr __at (0xBB) ADC0COM ; /* ADC 0 OFFSET CALIBRATION MIDDLE */
|
||||
__sfr __at (0xBC) ADC0COH ; /* ADC 0 OFFSET CALIBRATION HIGH */
|
||||
__sfr __at (0xBD) ADC0BUF ; /* ADC 0 BUFFER CONTROL */
|
||||
__sfr __at (0xBE) CLKMUL ; /* CLOCK MULTIPLIER */
|
||||
__sfr __at (0xBF) ADC0DAC ; /* ADC 0 OFFSET DAC */
|
||||
__sfr __at (0xC0) SMB0CN ; /* SMBUS CONTROL */
|
||||
__sfr __at (0xC1) SMB0CF ; /* SMBUS CONFIGURATION */
|
||||
__sfr __at (0xC2) SMB0DAT ; /* SMBUS DATA */
|
||||
__sfr __at (0xC3) ADC0L ; /* ADC 0 OUTPUT LOW BYTE */
|
||||
__sfr __at (0xC4) ADC0M ; /* ADC 0 OUTPUT MIDDLE BYTE */
|
||||
__sfr __at (0xC5) ADC0H ; /* ADC 0 OUTPUT HIGH BYTE */
|
||||
__sfr __at (0xC6) ADC0MUX ; /* ADC 0 MULTIPLEXER */
|
||||
__sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
|
||||
__sfr __at (0xC8) TMR2CN ; /* TIMER 2 CONTROL */
|
||||
__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at (0xCA) TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xCB) TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
|
||||
__sfr __at (0xCC) TMR2L ; /* TIMER 2 - LOW BYTE */
|
||||
__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
|
||||
__sfr __at (0xCD) TMR2H ; /* TIMER 2 - HIGH BYTE */
|
||||
__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
|
||||
__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
|
||||
__sfr __at (0xD4) P0SKIP ; /* PORT 0 SKIP */
|
||||
__sfr __at (0xD5) P1SKIP ; /* PORT 1 SKIP */
|
||||
__sfr __at (0xD7) IDA1CN ; /* CURRENT MODE DAC 1 - CONTROL */
|
||||
__sfr __at (0xD8) PCA0CN ; /* PCA CONTROL */
|
||||
__sfr __at (0xD9) PCA0MD ; /* PCA MODE */
|
||||
__sfr __at (0xDA) PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
|
||||
__sfr __at (0xDB) PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
|
||||
__sfr __at (0xDC) PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
|
||||
__sfr __at (0xDD) IDA1 ; /* CURRENT MODE DAC 1 */
|
||||
__sfr __at (0xE0) ACC ; /* ACCUMULATOR */
|
||||
__sfr __at (0xE1) XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
|
||||
__sfr __at (0xE2) XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
|
||||
__sfr __at (0xE3) PFE0CN ; /* PREFETCH ENGINE CONTROL */
|
||||
__sfr __at (0xE4) IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
|
||||
__sfr __at (0xE4) INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
|
||||
__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
|
||||
__sfr __at (0xE8) ADC0STA ; /* ADC 0 STATUS */
|
||||
__sfr __at (0xE9) PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
|
||||
__sfr __at (0xEA) PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
|
||||
__sfr __at (0xEB) PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
|
||||
__sfr __at (0xEC) PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
|
||||
__sfr __at (0xED) PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
|
||||
__sfr __at (0xEE) PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
|
||||
__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
|
||||
__sfr __at (0xF0) B ; /* B REGISTER */
|
||||
__sfr __at (0xF1) P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF1) P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF2) P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF2) P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xF3) ADC0MD ; /* ADC 0 MODE */
|
||||
__sfr __at (0xF4) ADC0CN ; /* ADC 0 CONTROL */
|
||||
__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
|
||||
__sfr __at (0xF7) ADC0CLK ; /* ADC 0 CLOCK */
|
||||
__sfr __at (0xF8) SPI0CN ; /* SPI0 CONTROL */
|
||||
__sfr __at (0xF9) PCA0L ; /* PCA COUNTER LOW */
|
||||
__sfr __at (0xFA) PCA0H ; /* PCA COUNTER HIGH */
|
||||
__sfr __at (0xFB) ADC0CF ; /* ADC 0 CONFIGURATION */
|
||||
__sfr __at (0xFC) ADC0FL ; /* ADC 0 FAST FILTER OUTPUT LOW */
|
||||
__sfr __at (0xFD) ADC0FM ; /* ADC 0 FAST FILTER OUTPUT MIDDLE */
|
||||
__sfr __at (0xFE) ADC0FH ; /* ADC 0 FAST FILTER OUTPUT HIGH */
|
||||
__sfr __at (0xFF) VDM0CN ; /* VDD MONITOR CONTROL */
|
||||
|
||||
|
||||
/* WORD/DWORD Registers */
|
||||
|
||||
__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
|
||||
__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
|
||||
__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
|
||||
__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
|
||||
__sfr16 __at (0xCBCA) TMR2RL ; /* TIMER 2 CAPTURE REGISTER WORD */
|
||||
__sfr16 __at (0x9594) TMR3 ; /* TIMER 3 COUNTER */
|
||||
__sfr16 __at (0x9392) TMR3RL ; /* TIMER 3 CAPTURE REGISTER WORD */
|
||||
|
||||
__sfr16 __at (0x9B9A) ADC0DEC ; /* ADC 0 DECIMATION RATIO REGISTER WORD */
|
||||
/* Unfortunately the C8051F350 does not have an sfr that always reads 0x00 and */
|
||||
/* ignores what is written to it. That could have enabled sfr32 definitions for */
|
||||
/* the 24 bit ADC0 sfr combinations. */
|
||||
__sfr16 __at (0xC5C4) ADC0 ; /* 16 bit ADC 0 SINC3 FILTER OUTPUT WORD */
|
||||
__sfr16 __at (0xFEFD) ADC0F ; /* 16 bit ADC 0 FAST FILTER OUTPUT WORD */
|
||||
|
||||
__sfr16 __at (0xFAF9) PCA0 ; /* PCA COUNTER */
|
||||
__sfr16 __at (0xEAE9) PCA0CP0 ; /* PCA CAPTURE 0 WORD */
|
||||
__sfr16 __at (0xECEB) PCA0CP1 ; /* PCA CAPTURE 1 WORD */
|
||||
__sfr16 __at (0xEEED) PCA0CP2 ; /* PCA CAPTURE 2 WORD */
|
||||
|
||||
|
||||
/* BIT Registers */
|
||||
|
||||
/* P0 0x80 */
|
||||
__sbit __at (0x80) P0_0 ;
|
||||
__sbit __at (0x81) P0_1 ;
|
||||
__sbit __at (0x82) P0_2 ;
|
||||
__sbit __at (0x83) P0_3 ;
|
||||
__sbit __at (0x84) P0_4 ;
|
||||
__sbit __at (0x85) P0_5 ;
|
||||
__sbit __at (0x86) P0_6 ;
|
||||
__sbit __at (0x87) P0_7 ;
|
||||
|
||||
/* TCON 0x88 */
|
||||
__sbit __at (0x88) IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
|
||||
__sbit __at (0x89) IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
|
||||
__sbit __at (0x8A) IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
|
||||
__sbit __at (0x8B) IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
|
||||
__sbit __at (0x8C) TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
|
||||
__sbit __at (0x8D) TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
|
||||
__sbit __at (0x8E) TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
|
||||
__sbit __at (0x8F) TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
|
||||
|
||||
/* P1 0x90 */
|
||||
__sbit __at (0x90) P1_0 ;
|
||||
__sbit __at (0x91) P1_1 ;
|
||||
__sbit __at (0x92) P1_2 ;
|
||||
__sbit __at (0x93) P1_3 ;
|
||||
__sbit __at (0x94) P1_4 ;
|
||||
__sbit __at (0x95) P1_5 ;
|
||||
__sbit __at (0x96) P1_6 ;
|
||||
__sbit __at (0x97) P1_7 ;
|
||||
|
||||
/* SCON 0x98 */
|
||||
__sbit __at (0x98) RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
|
||||
__sbit __at (0x98) RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
|
||||
__sbit __at (0x99) TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
|
||||
__sbit __at (0x99) TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
|
||||
__sbit __at (0x9A) RB8 ; /* SCON.2 - RECEIVE BIT 8 */
|
||||
__sbit __at (0x9A) RB80 ; /* SCON.2 - RECEIVE BIT 8 */
|
||||
__sbit __at (0x9B) TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
|
||||
__sbit __at (0x9B) TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
|
||||
__sbit __at (0x9C) REN ; /* SCON.4 - RECEIVE ENABLE */
|
||||
__sbit __at (0x9C) REN0 ; /* SCON.4 - RECEIVE ENABLE */
|
||||
__sbit __at (0x9D) SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
|
||||
__sbit __at (0x9D) MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
|
||||
__sbit __at (0x9F) SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
|
||||
__sbit __at (0x9F) S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
|
||||
|
||||
/* P2 0xA0 */
|
||||
__sbit __at (0xA0) P2_0 ;
|
||||
__sbit __at (0xA1) P2_1 ;
|
||||
__sbit __at (0xA2) P2_2 ;
|
||||
__sbit __at (0xA3) P2_3 ;
|
||||
__sbit __at (0xA4) P2_4 ;
|
||||
__sbit __at (0xA5) P2_5 ;
|
||||
__sbit __at (0xA6) P2_6 ;
|
||||
__sbit __at (0xA7) P2_7 ;
|
||||
|
||||
/* IE 0xA8 */
|
||||
__sbit __at (0xA8) EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
|
||||
__sbit __at (0xA9) ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAA) EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
|
||||
__sbit __at (0xAB) ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAC) ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
|
||||
__sbit __at (0xAC) ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
|
||||
__sbit __at (0xAD) ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAE) ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */
|
||||
__sbit __at (0xAF) EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
|
||||
|
||||
/* IP 0xB8 */
|
||||
__sbit __at (0xB8) PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
|
||||
__sbit __at (0xB9) PT0 ; /* IP.1 - TIMER 0 PRIORITY */
|
||||
__sbit __at (0xBA) PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
|
||||
__sbit __at (0xBB) PT1 ; /* IP.3 - TIMER 1 PRIORITY */
|
||||
__sbit __at (0xBC) PS ; /* IP.4 - SERIAL PORT PRIORITY */
|
||||
__sbit __at (0xBC) PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
|
||||
__sbit __at (0xBD) PT2 ; /* IP.5 - TIMER 2 PRIORITY */
|
||||
__sbit __at (0xBE) PSPI0 ; /* IP.6 - SPI0 PRIORITY */
|
||||
|
||||
/* SMB0CN 0xC0 */
|
||||
__sbit __at (0xC0) SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
|
||||
__sbit __at (0xC1) ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
|
||||
__sbit __at (0xC2) ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
|
||||
__sbit __at (0xC3) ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
|
||||
__sbit __at (0xC4) STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
|
||||
__sbit __at (0xC5) STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
|
||||
__sbit __at (0xC6) TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
|
||||
__sbit __at (0xC7) MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
|
||||
|
||||
/* TMR2CN 0xC8 */
|
||||
__sbit __at (0xC8) T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
|
||||
__sbit __at (0xCA) TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
|
||||
__sbit __at (0xCB) T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
|
||||
__sbit __at (0xCC) TF2CEN ; /* TMR2CN.4 - TIMER 2 LOW-FREQ OSC CAPTURE ENABLE*/
|
||||
__sbit __at (0xCD) TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
|
||||
__sbit __at (0xCE) TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
|
||||
__sbit __at (0xCF) TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
|
||||
__sbit __at (0xCF) TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
|
||||
|
||||
/* PSW 0xD0 */
|
||||
__sbit __at (0xD0) PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
|
||||
__sbit __at (0xD1) F1 ; /* PSW.1 - FLAG 1 */
|
||||
__sbit __at (0xD2) OV ; /* PSW.2 - OVERFLOW FLAG */
|
||||
__sbit __at (0xD3) RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
|
||||
__sbit __at (0xD4) RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
|
||||
__sbit __at (0xD5) F0 ; /* PSW.5 - FLAG 0 */
|
||||
__sbit __at (0xD6) AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
|
||||
__sbit __at (0xD7) CY ; /* PSW.7 - CARRY FLAG */
|
||||
|
||||
/* PCA0CN 0xD8 */
|
||||
__sbit __at (0xD8) CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
|
||||
__sbit __at (0xD9) CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
|
||||
__sbit __at (0xDA) CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
|
||||
__sbit __at (0xDE) CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
|
||||
__sbit __at (0xDF) CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
|
||||
|
||||
/* ADC0STA 0xE8 */
|
||||
__sbit __at (0xE8) AD0OVR ; /* ADC0CN.0 - ADC 0 OVERRUN FLAG */
|
||||
__sbit __at (0xE9) AD0ERR ; /* ADC0CN.1 - ADC 0 ERROR FLAG */
|
||||
__sbit __at (0xEA) AD0CALC ; /* ADC0CN.2 - ADC 0 CALIBRATION COMPLETE FLAG */
|
||||
__sbit __at (0xEB) AD0FFC ; /* ADC0CN.3 - ADC 0 FAST FILTER CLIP FLAG */
|
||||
__sbit __at (0xEC) AD0S3C ; /* ADC0CN.4 - ADC 0 SINC3 FILTER CLIP FLAG */
|
||||
__sbit __at (0xED) AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
|
||||
__sbit __at (0xEE) AD0CBSY ; /* ADC0CN.6 - ADC 0 CALIBRATION IN PROGRESS FLAG */
|
||||
__sbit __at (0xEF) AD0BUSY ; /* ADC0CN.7 - ADC 0 CONVERSION IN PROGRESS FLAG */
|
||||
|
||||
/* SPI0CN 0xF8 */
|
||||
__sbit __at (0xF8) SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */
|
||||
__sbit __at (0xF9) TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
|
||||
__sbit __at (0xFA) NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
|
||||
__sbit __at (0xFB) NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
|
||||
__sbit __at (0xFC) RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
|
||||
__sbit __at (0xFD) MODF ; /* SPI0CN.5 - MODE FAULT FLAG */
|
||||
__sbit __at (0xFE) WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */
|
||||
__sbit __at (0xFF) SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
|
||||
|
||||
|
||||
/* Predefined SFR Bit Masks */
|
||||
|
||||
#define PCON_IDLE 0x01 /* PCON */
|
||||
#define PCON_STOP 0x02 /* PCON */
|
||||
#define T1M 0x08 /* CKCON */
|
||||
#define PSWE 0x01 /* PSCTL */
|
||||
#define PSEE 0x02 /* PSCTL */
|
||||
#define ECP0 0x20 /* EIE1 */
|
||||
#define PORSF 0x02 /* RSTSRC */
|
||||
#define SWRSF 0x10 /* RSTSRC */
|
||||
#define ECCF 0x01 /* PCA0CPMn */
|
||||
#define PWM 0x02 /* PCA0CPMn */
|
||||
#define TOG 0x04 /* PCA0CPMn */
|
||||
#define MAT 0x08 /* PCA0CPMn */
|
||||
#define CAPN 0x10 /* PCA0CPMn */
|
||||
#define CAPP 0x20 /* PCA0CPMn */
|
||||
#define ECOM 0x40 /* PCA0CPMn */
|
||||
#define PWM16 0x80 /* PCA0CPMn */
|
||||
#define CP0E 0x10 /* XBR0 */
|
||||
#define CP0OEN 0x10 /* XBR0 */
|
||||
#define CP0AE 0x20 /* XBR0 */
|
||||
#define CP0AOEN 0x20 /* XBR0 */
|
||||
|
||||
#endif
|
||||
362
lib/mcs51/C8051F360.h
Normal file
362
lib/mcs51/C8051F360.h
Normal file
@@ -0,0 +1,362 @@
|
||||
/*-------------------------------------------------------------------------
|
||||
C8051F360.h - Register Declarations for the SiLabs C8051F36x
|
||||
Processor Range
|
||||
|
||||
Copyright (C) 2007, Maarten Brock, sourceforge.brock@dse.nl
|
||||
|
||||
This library is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the
|
||||
Free Software Foundation; either version 2, or (at your option) any
|
||||
later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this library; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
|
||||
MA 02110-1301, USA.
|
||||
|
||||
As a special exception, if you link this library with other files,
|
||||
some of which are compiled with SDCC, to produce an executable,
|
||||
this library does not by itself cause the resulting executable to
|
||||
be covered by the GNU General Public License. This exception does
|
||||
not however invalidate any other reasons why the executable file
|
||||
might be covered by the GNU General Public License.
|
||||
-------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef C8051F360_H
|
||||
#define C8051F360_H
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
/* All Pages */
|
||||
|
||||
SFR(P0, 0x80); // Port 0
|
||||
SBIT(P0_0, 0x80, 0); // Port 0 bit 0
|
||||
SBIT(P0_1, 0x80, 1); // Port 0 bit 1
|
||||
SBIT(P0_2, 0x80, 2); // Port 0 bit 2
|
||||
SBIT(P0_3, 0x80, 3); // Port 0 bit 3
|
||||
SBIT(P0_4, 0x80, 4); // Port 0 bit 4
|
||||
SBIT(P0_5, 0x80, 5); // Port 0 bit 5
|
||||
SBIT(P0_6, 0x80, 6); // Port 0 bit 6
|
||||
SBIT(P0_7, 0x80, 7); // Port 0 bit 7
|
||||
SFR(SP, 0x81); // Stack Pointer
|
||||
SFR(DPL, 0x82); // Data Pointer Low Byte
|
||||
SFR(DPH, 0x83); // Data Pointer High Byte
|
||||
SFR(SFRNEXT, 0x85); // SFR Stack Next Page
|
||||
SFR(SFRLAST, 0x86); // SFR Stack Last Page
|
||||
SFR(PCON, 0x87); // Power Mode Control
|
||||
SFR(TCON, 0x88); // Timer Control
|
||||
SBIT(IT0, 0x88, 0); // Ext. Interrupt 0 Type Select
|
||||
SBIT(IE0, 0x88, 1); // Ext. Interrupt 0 Flag
|
||||
SBIT(IT1, 0x88, 2); // Ext. Interrupt 1 Type Select
|
||||
SBIT(IE1, 0x88, 3); // Ext. Interrupt 1 Flag
|
||||
SBIT(TR0, 0x88, 4); // Timer 0 Run Control
|
||||
SBIT(TF0, 0x88, 5); // Timer 0 Overflow Flag
|
||||
SBIT(TR1, 0x88, 6); // Timer 1 Run Control
|
||||
SBIT(TF1, 0x88, 7); // Timer 1 Overflow Flag
|
||||
SFR(TMOD, 0x89); // Timer Mode
|
||||
SFR16E(TMR0, 0x8C8A); // Timer/Counter 0 Word
|
||||
SFR(TL0, 0x8A); // Timer/Counter 0 Low Byte
|
||||
SFR(TH0, 0x8C); // Timer/Counter 0 High Byte
|
||||
SFR16E(TMR1, 0x8D8B); // Timer/Counter 1 Word
|
||||
SFR(TL1, 0x8B); // Timer/Counter 1 Low Byte
|
||||
SFR(TH1, 0x8D); // Timer/Counter 1 High Byte
|
||||
SFR(CKCON, 0x8E); // Clock Control
|
||||
SFR(P1, 0x90); // Port 1
|
||||
SBIT(P1_0, 0x90, 0); // Port 1 bit 0
|
||||
SBIT(P1_1, 0x90, 1); // Port 1 bit 1
|
||||
SBIT(P1_2, 0x90, 2); // Port 1 bit 2
|
||||
SBIT(P1_3, 0x90, 3); // Port 1 bit 3
|
||||
SBIT(P1_4, 0x90, 4); // Port 1 bit 4
|
||||
SBIT(P1_5, 0x90, 5); // Port 1 bit 5
|
||||
SBIT(P1_6, 0x90, 6); // Port 1 bit 6
|
||||
SBIT(P1_7, 0x90, 7); // Port 1 bit 7
|
||||
SFR(TMR3CN, 0x91); // Timer 3 Control
|
||||
SFR16(TMR3RL, 0x92); // Timer 3 Reload Register Word
|
||||
SFR(TMR3RLL, 0x92); // Timer 3 Reload Register Low Byte
|
||||
SFR(TMR3RLH, 0x93); // Timer 3 Reload Register High Byte
|
||||
SFR16(TMR3, 0x94); // Timer 3 Word
|
||||
SFR(TMR3L, 0x94); // Timer 3 Low Byte
|
||||
SFR(TMR3H, 0x95); // Timer 3 High Byte
|
||||
SFR16(IDA0, 0x96); // IDAC 0 Word
|
||||
SFR(IDA0L, 0x96); // IDAC 0 Low Byte
|
||||
SFR(IDA0H, 0x97); // IDAC 0 High Byte
|
||||
SFR(SCON0, 0x98); // Serial Port 0 Control
|
||||
SBIT(RI0, 0x98, 0); // Receive Interrupt Flag
|
||||
SBIT(TI0, 0x98, 1); // Transmit Interrupt Flag
|
||||
SBIT(RB80, 0x98, 2); // Ninth Receive Bit
|
||||
SBIT(TB80, 0x98, 3); // Ninth Transmission Bit
|
||||
SBIT(REN0, 0x98, 4); // Receive Enable
|
||||
SBIT(MCE0, 0x98, 5); // Multiprocessor Communication Enable
|
||||
SBIT(S0MODE, 0x98, 7); // Serial Port 0 Operation Mode
|
||||
SFR(SBUF0, 0x99); // Serial Port 0 Data Buffer
|
||||
SFR(CPT1CN, 0x9A); // Comparator 1 Control
|
||||
SFR(CPT0CN, 0x9B); // Comparator 0 Control
|
||||
SFR(CPT1MD, 0x9C); // Comparator 1 Mode Selection
|
||||
SFR(CPT0MD, 0x9D); // Comparator 0 Mode Selection
|
||||
SFR(CPT1MX, 0x9E); // Comparator 1 MUX Selection
|
||||
SFR(CPT0MX, 0x9F); // Comparator 0 MUX Selection
|
||||
SFR(P2, 0xA0); // Port 2
|
||||
SBIT(P2_0, 0xA0, 0); // Port 2 bit 0
|
||||
SBIT(P2_1, 0xA0, 1); // Port 2 bit 1
|
||||
SBIT(P2_2, 0xA0, 2); // Port 2 bit 2
|
||||
SBIT(P2_3, 0xA0, 3); // Port 2 bit 3
|
||||
SBIT(P2_4, 0xA0, 4); // Port 2 bit 4
|
||||
SBIT(P2_5, 0xA0, 5); // Port 2 bit 5
|
||||
SBIT(P2_6, 0xA0, 6); // Port 2 bit 6
|
||||
SBIT(P2_7, 0xA0, 7); // Port 2 bit 7
|
||||
SFR(SPI0CFG, 0xA1); // SPI Configuration
|
||||
SFR(SPI0CKR, 0xA2); // SPI Clock Rate Control
|
||||
SFR(SPI0DAT, 0xA3); // SPI Data
|
||||
SFR(SFRPAGE, 0xA7); // SFR Page Select
|
||||
SFR(IE, 0xA8); // Interrupt Enable
|
||||
SBIT(EX0, 0xA8, 0); // Enable External Interrupt 0
|
||||
SBIT(ET0, 0xA8, 1); // Enable Timer 0 Interrupt
|
||||
SBIT(EX1, 0xA8, 2); // Enable External Interrupt 1
|
||||
SBIT(ET1, 0xA8, 3); // Enable Timer 1 Interrupt
|
||||
SBIT(ES0, 0xA8, 4); // Enable Serial Port Interrupt
|
||||
SBIT(ET2, 0xA8, 5); // Enable Timer 2 Interrupt
|
||||
SBIT(ESPI0, 0xA8, 6); // Enable SPI0 Interrupt
|
||||
SBIT(EA, 0xA8, 7); // Global Interrupt Enable
|
||||
SFR(EMI0CN, 0xAA); // EMIF Control
|
||||
SFR(_XPAGE, 0xAA); // SDCC: XDATA/PDATA Page
|
||||
SFR(P3, 0xB0); // Port 3
|
||||
SBIT(P3_0, 0xB0, 0); // Port 3 bit 0
|
||||
SBIT(P3_1, 0xB0, 1); // Port 3 bit 1
|
||||
SBIT(P3_2, 0xB0, 2); // Port 3 bit 2
|
||||
SBIT(P3_3, 0xB0, 3); // Port 3 bit 3
|
||||
SBIT(P3_4, 0xB0, 4); // Port 3 bit 4
|
||||
SBIT(P3_5, 0xB0, 5); // Port 3 bit 5
|
||||
SBIT(P3_6, 0xB0, 6); // Port 3 bit 6
|
||||
SBIT(P3_7, 0xB0, 7); // Port 3 bit 7
|
||||
SFR(P4, 0xB5); // Port 4
|
||||
SFR(IP, 0xB8); // Interrupt Priority
|
||||
SBIT(PX0, 0xB8, 0); // External Interrupt 0 Priority
|
||||
SBIT(PT0, 0xB8, 1); // Timer 0 Interrupt Priority
|
||||
SBIT(PX1, 0xB8, 2); // External Interrupt 1 Priority
|
||||
SBIT(PT1, 0xB8, 3); // Timer 1 Interrupt Priority
|
||||
SBIT(PS0, 0xB8, 4); // Serial Port Interrupt Priority
|
||||
SBIT(PT2, 0xB8, 5); // Timer 2 Interrupt Priority
|
||||
SBIT(PSPI0, 0xB8, 6); // SPI0 Interrupt Priority
|
||||
SFR(IDA0CN, 0xB9); // IDAC 0 Control
|
||||
SFR(AMX0N, 0xBA); // AMUX 0 Negative Channel Select
|
||||
SFR(AMX0P, 0xBB); // AMUX 0 Positive Channel Select
|
||||
SFR(ADC0CF, 0xBC); // ADC0 Configuration
|
||||
SFR16(ADC0, 0xBD); // ADC0 Word
|
||||
SFR(ADC0L, 0xBD); // ADC0 Low Byte
|
||||
SFR(ADC0H, 0xBE); // ADC0 High Byte
|
||||
SFR(SMB0CN, 0xC0); // SMBus Control
|
||||
SBIT(SI, 0xC0, 0); // SMBus Interrupt Flag
|
||||
SBIT(ACK, 0xC0, 1); // SMBus Acknowledge Flag
|
||||
SBIT(ARBLOST, 0xC0, 2); // SMBus Arbitration Lost Indicator
|
||||
SBIT(ACKRQ, 0xC0, 3); // SMBus Acknowledge Request
|
||||
SBIT(STO, 0xC0, 4); // SMBus Stop Flag
|
||||
SBIT(STA, 0xC0, 5); // SMBus Start Flag
|
||||
SBIT(TXMODE, 0xC0, 6); // SMBus Transmit Mode Indicator
|
||||
SBIT(MASTER, 0xC0, 7); // SMBus Master/Slave Indicator
|
||||
SFR(SMB0CF, 0xC1); // SMBus Configuration
|
||||
SFR(SMB0DAT, 0xC2); // SMBus Data
|
||||
SFR16(ADC0GT, 0xC3); // ADC0 Greater-Than Data Word
|
||||
SFR(ADC0GTL, 0xC3); // ADC0 Greater-Than Data Low Byte
|
||||
SFR(ADC0GTH, 0xC4); // ADC0 Greater-Than Data High Byte
|
||||
SFR16(ADC0LT, 0xC5); // ADC0 Less-Than Data Word
|
||||
SFR(ADC0LTL, 0xC5); // ADC0 Less-Than Data Low Byte
|
||||
SFR(ADC0LTH, 0xC6); // ADC0 Less-Than Data High Byte
|
||||
SFR(TMR2CN, 0xC8); // Timer/Counter 2 Control
|
||||
SBIT(T2XCLK, 0xC8, 0); // Timer 2 External Clock Select
|
||||
SBIT(TR2, 0xC8, 2); // Timer 2 Run Control
|
||||
SBIT(T2SPLIT, 0xC8, 3); // Timer 2 Split Mode Enable
|
||||
SBIT(TF2CEN, 0xC8, 4); // Timer 2 Low-Frequency Oscillator Capture Enable
|
||||
SBIT(TF2LEN, 0xC8, 5); // Timer 2 Low Byte Interrupt Enable
|
||||
SBIT(TF2L, 0xC8, 6); // Timer 2 Low Byte Overflow Flag
|
||||
SBIT(TF2H, 0xC8, 7); // Timer 2 High Byte Overflow Flag
|
||||
SFR16(TMR2RL, 0xCA); // Timer/Counter 2 Reload Word
|
||||
SFR(TMR2RLL, 0xCA); // Timer/Counter 2 Reload Low Byte
|
||||
SFR(TMR2RLH, 0xCB); // Timer/Counter 2 Reload High Byte
|
||||
SFR16(TMR2, 0xCC); // Timer/Counter 2 Word
|
||||
SFR(TMR2L, 0xCC); // Timer/Counter 2 Low Byte
|
||||
SFR(TMR2H, 0xCD); // Timer/Counter 2 High Byte
|
||||
SFR(PSW, 0xD0); // Program Status Word
|
||||
SBIT(P, 0xD0, 0); // Parity Flag
|
||||
SBIT(F1, 0xD0, 1); // User-Defined Flag
|
||||
SBIT(OV, 0xD0, 2); // Overflow Flag
|
||||
SBIT(RS0, 0xD0, 3); // Register Bank Select 0
|
||||
SBIT(RS1, 0xD0, 4); // Register Bank Select 1
|
||||
SBIT(F0, 0xD0, 5); // User-Defined Flag
|
||||
SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag
|
||||
SBIT(CY, 0xD0, 7); // Carry Flag
|
||||
SFR(REF0CN, 0xD1); // Voltage Reference Control
|
||||
SFR(PCA0CN, 0xD8); // PCA Control
|
||||
SBIT(CCF0, 0xD8, 0); // PCA Module 0 Capture/Compare Flag
|
||||
SBIT(CCF1, 0xD8, 1); // PCA Module 1 Capture/Compare Flag
|
||||
SBIT(CCF2, 0xD8, 2); // PCA Module 2 Capture/Compare Flag
|
||||
SBIT(CCF3, 0xD8, 3); // PCA Module 3 Capture/Compare Flag
|
||||
SBIT(CCF4, 0xD8, 4); // PCA Module 4 Capture/Compare Flag
|
||||
SBIT(CCF5, 0xD8, 5); // PCA Module 5 Capture/Compare Flag
|
||||
SBIT(CR, 0xD8, 6); // PCA Counter/Timer Run Control
|
||||
SBIT(CF, 0xD8, 7); // PCA Counter/Timer Overflow Flag
|
||||
SFR(PCA0MD, 0xD9); // PCA Mode
|
||||
SFR(PCA0CPM0, 0xDA); // PCA Module 0 Mode
|
||||
SFR(PCA0CPM1, 0xDB); // PCA Module 1 Mode
|
||||
SFR(PCA0CPM2, 0xDC); // PCA Module 2 Mode
|
||||
SFR(PCA0CPM3, 0xDD); // PCA Module 3 Mode
|
||||
SFR(PCA0CPM4, 0xDE); // PCA Module 4 Mode
|
||||
SFR(PCA0CPM5, 0xDF); // PCA Module 5 Mode
|
||||
SFR(ACC, 0xE0); // Accumulator
|
||||
SFR(IT01CF, 0xE4); // INT0/INT1 Configuration
|
||||
SFR(EIE1, 0xE6); // Extended Interrupt Enable 1
|
||||
SFR(EIE2, 0xE7); // Extended Interrupt Enable 2
|
||||
SFR(ADC0CN, 0xE8); // ADC0 Control
|
||||
SBIT(AD0CM0, 0xE8, 0); // ADC0 Conversion Start Mode Select Bit 0
|
||||
SBIT(AD0CM1, 0xE8, 1); // ADC0 Conversion Start Mode Select Bit 1
|
||||
SBIT(AD0CM2, 0xE8, 2); // ADC0 Conversion Start Mode Select Bit 2
|
||||
SBIT(AD0WINT, 0xE8, 3); // ADC0 Window Compare Interrupt Flag
|
||||
SBIT(AD0BUSY, 0xE8, 4); // ADC0 Busy Bit
|
||||
SBIT(AD0INT, 0xE8, 5); // ADC0 Conversion Complete Interrupt Flag
|
||||
SBIT(AD0TM, 0xE8, 6); // ADC0 Track Mode Bit
|
||||
SBIT(AD0EN, 0xE8, 7); // ADC0 Enable Bit
|
||||
SFR16(PCA0CP1, 0xE9); // PCA Capture 1 Word
|
||||
SFR(PCA0CPL1, 0xE9); // PCA Capture 1 Low Byte
|
||||
SFR(PCA0CPH1, 0xEA); // PCA Capture 1 High Byte
|
||||
SFR16(PCA0CP2, 0xEB); // PCA Capture 2 Word
|
||||
SFR(PCA0CPL2, 0xEB); // PCA Capture 2 Low Byte
|
||||
SFR(PCA0CPH2, 0xEC); // PCA Capture 2 High Byte
|
||||
SFR16(PCA0CP3, 0xED); // PCA Capture 3 Word
|
||||
SFR(PCA0CPL3, 0xED); // PCA Capture 3 Low Byte
|
||||
SFR(PCA0CPH3, 0xEE); // PCA Capture 3 High Byte
|
||||
SFR(RSTSRC, 0xEF); // Reset Source Configuration/Status
|
||||
SFR(B, 0xF0); // B Register
|
||||
SFR16(PCA0CP5, 0xF5); // PCA Capture 5 Word
|
||||
SFR(PCA0CPL5, 0xF5); // PCA Capture 5 Low Byte
|
||||
SFR(PCA0CPH5, 0xF6); // PCA Capture 5 High Byte
|
||||
SFR(SPI0CN, 0xF8); // SPI0 Control
|
||||
SBIT(SPIEN, 0xF8, 0); // SPI0 Enable
|
||||
SBIT(TXBMT, 0xF8, 1); // SPI0 Transmit Buffer Empty
|
||||
SBIT(NSSMD0, 0xF8, 2); // SPI0 Slave Select Mode Bit 0
|
||||
SBIT(NSSMD1, 0xF8, 3); // SPI0 Slave Select Mode Bit 1
|
||||
SBIT(RXOVRN, 0xF8, 4); // SPI0 Receive Overrun Flag
|
||||
SBIT(MODF, 0xF8, 5); // SPI0 Mode Fault Flag
|
||||
SBIT(WCOL, 0xF8, 6); // SPI0 Write Collision Flag
|
||||
SBIT(SPIF, 0xF8, 7); // SPI0 Interrupt Flag
|
||||
SFR16(PCA0, 0xF9); // PCA Counter Word
|
||||
SFR(PCA0L, 0xF9); // PCA Counter Low Byte
|
||||
SFR(PCA0H, 0xFA); // PCA Counter High Byte
|
||||
SFR16(PCA0CP0, 0xFB); // PCA Capture 0 Word
|
||||
SFR(PCA0CPL0, 0xFB); // PCA Capture 0 Low Byte
|
||||
SFR(PCA0CPH0, 0xFC); // PCA Capture 0 High Byte
|
||||
SFR16(PCA0CP4, 0xFD); // PCA Capture 4 Word
|
||||
SFR(PCA0CPL4, 0xFD); // PCA Capture 4 Low Byte
|
||||
SFR(PCA0CPH4, 0xFE); // PCA Capture 4 High Byte
|
||||
SFR(VDM0CN, 0xFF); // VDD Monitor Control
|
||||
|
||||
/* Page 0x00 */
|
||||
|
||||
SFR(PSCTL, 0x8F); // Program Store R/W Control
|
||||
SFR16(MAC0A, 0xA4); // MAC0 A Register Word
|
||||
SFR(MAC0AL, 0xA4); // MAC0 A Register Low Byte
|
||||
SFR(MAC0AH, 0xA5); // MAC0 A Register High Byte
|
||||
SFR16(MAC0RND, 0xAE); // MAC0 Rounding Register Word
|
||||
SFR(MAC0RNDL, 0xAE); // MAC0 Rounding Register Low Byte
|
||||
SFR(MAC0RNDH, 0xAF); // MAC0 Rounding Register High Byte
|
||||
SFR(P2MAT, 0xB1); // Port 2 Match
|
||||
SFR(P2MASK, 0xB2); // Port 2 Mask
|
||||
SFR(FLSCL, 0xB6); // Flash Scale
|
||||
SFR(FLKEY, 0xB7); // Flash Lock and Key
|
||||
SFR(MAC0STA, 0xCF); // MAC0 Status Register
|
||||
SFR32(MAC0ACC, 0xD2); // MAC0 Accumulator Long Word
|
||||
SFR(MAC0ACC0, 0xD2); // MAC0 Accumulator Byte 0 (LSB)
|
||||
SFR(MAC0ACC1, 0xD3); // MAC0 Accumulator Byte 1
|
||||
SFR(MAC0ACC2, 0xD4); // MAC0 Accumulator Byte 2
|
||||
SFR(MAC0ACC3, 0xD5); // MAC0 Accumulator Byte 3 (MSB)
|
||||
SFR(MAC0OVR, 0xD6); // MAC0 Accumulator Overflow
|
||||
SFR(MAC0CF, 0xD7); // MAC0 Configuration
|
||||
SFR(P1MAT, 0xE1); // Port 1 Match
|
||||
SFR(P1MASK, 0xE2); // Port 1 Mask
|
||||
// No sfr16 definition for MAC0B because MAC0BL must be written last
|
||||
SFR(MAC0BL, 0xF1); // MAC0 B Register Low Byte
|
||||
SFR(MAC0BH, 0xF2); // MAC0 B Register High Byte
|
||||
SFR(P0MAT, 0xF3); // Port 0 Match
|
||||
SFR(P0MASK, 0xF4); // Port 0 Mask
|
||||
|
||||
/* Page 0x0F */
|
||||
|
||||
SFR(CCH0CN, 0x84); // Cache Control
|
||||
SFR(CLKSEL, 0x8F); // Clock Select
|
||||
SFR(P0MDOUT, 0xA4); // Port 0 Output Mode Configuration
|
||||
SFR(P1MDOUT, 0xA5); // Port 1 Output Mode Configuration
|
||||
SFR(P2MDOUT, 0xA6); // Port 2 Output Mode Configuration
|
||||
SFR(PLL0DIV, 0xA9); // PLL Divider
|
||||
SFR(FLSTAT, 0xAC); // Flash Status
|
||||
SFR(OSCLCN, 0xAD); // Internal Low-Frequency Oscillator Control
|
||||
SFR(P4MDOUT, 0xAE); // Port 4 Output Mode Configuration
|
||||
SFR(P3MDOUT, 0xAF); // Port 3 Output Mode Configuration
|
||||
SFR(PLL0MUL, 0xB1); // PLL Multiplier
|
||||
SFR(PLL0FLT, 0xB2); // PLL Filter
|
||||
SFR(PLL0CN, 0xB3); // PLL Control
|
||||
SFR(OSCXCN, 0xB6); // External Oscillator Control
|
||||
SFR(OSCICN, 0xB7); // Internal Oscillator Control
|
||||
SFR(OSCICL, 0xBF); // Internal Oscillator Calibration
|
||||
SFR(EMI0CF, 0xC7); // EMIF Configuration
|
||||
SFR(CCH0TN, 0xC9); // Cache Tuning
|
||||
SFR(EIP1, 0xCE); // Extended Interrupt Priority 1
|
||||
SFR(EIP2, 0xCF); // Extended Interrupt Priority 2
|
||||
SFR(CCH0LC, 0xD2); // Cache Lock
|
||||
SFR(CCH0MA, 0xD3); // Cache Miss Accumulator
|
||||
SFR(P0SKIP, 0xD4); // Port 0 Skip
|
||||
SFR(P1SKIP, 0xD5); // Port 1 Skip
|
||||
SFR(P2SKIP, 0xD6); // Port 2 Skip
|
||||
SFR(P3SKIP, 0xD7); // Port 3 Skip
|
||||
SFR(XBR0, 0xE1); // Port I/O Crossbar Control 0
|
||||
SFR(XBR1, 0xE2); // Port I/O Crossbar Control 1
|
||||
SFR(SFR0CN, 0xE5); // SFR Page Control
|
||||
SFR(P0MDIN, 0xF1); // Port 0 Input Mode Configuration
|
||||
SFR(P1MDIN, 0xF2); // Port 1 Input Mode Configuration
|
||||
SFR(P2MDIN, 0xF3); // Port 2 Input Mode Configuration
|
||||
SFR(P3MDIN, 0xF4); // Port 3 Input Mode Configuration
|
||||
SFR(EMI0TC, 0xF7); // EMIF Timing Control
|
||||
|
||||
/* Predefined SFR Bit Masks */
|
||||
|
||||
#define PCON_IDLE 0x01 /* PCON */
|
||||
#define PCON_STOP 0x02 /* PCON */
|
||||
#define T1M 0x08 /* CKCON */
|
||||
#define PSWE 0x01 /* PSCTL */
|
||||
#define PSEE 0x02 /* PSCTL */
|
||||
#define PORSF 0x02 /* RSTSRC */
|
||||
#define SWRSF 0x10 /* RSTSRC */
|
||||
#define ECCF 0x01 /* PCA0CPMn */
|
||||
#define PWM 0x02 /* PCA0CPMn */
|
||||
#define TOG 0x04 /* PCA0CPMn */
|
||||
#define MAT 0x08 /* PCA0CPMn */
|
||||
#define CAPN 0x10 /* PCA0CPMn */
|
||||
#define CAPP 0x20 /* PCA0CPMn */
|
||||
#define ECOM 0x40 /* PCA0CPMn */
|
||||
#define PWM16 0x80 /* PCA0CPMn */
|
||||
#define CP0E 0x10 /* XBR0 */
|
||||
#define CP0AE 0x20 /* XBR0 */
|
||||
|
||||
/* Interrupts */
|
||||
|
||||
#define INT_EXT0 0 // External Interrupt 0
|
||||
#define INT_TIMER0 1 // Timer0 Overflow
|
||||
#define INT_EXT1 2 // External Interrupt 1
|
||||
#define INT_TIMER1 3 // Timer1 Overflow
|
||||
#define INT_UART0 4 // Serial Port 0
|
||||
#define INT_TIMER2 5 // Timer2 Overflow
|
||||
#define INT_SPI0 6 // Serial Peripheral Interface 0
|
||||
#define INT_SMBUS0 7 // SMBus0 Interface
|
||||
// 8 Reserved
|
||||
#define INT_ADC0_WINDOW 9 // ADC0 Window Comparison
|
||||
#define INT_ADC0_EOC 10 // ADC0 End Of Conversion
|
||||
#define INT_PCA0 11 // PCA0 Peripheral
|
||||
#define INT_COMPARATOR0 12 // Comparator0
|
||||
#define INT_COMPARATOR1 13 // Comparator1
|
||||
#define INT_TIMER3 14 // Timer3 Overflow
|
||||
// 15 Reserved
|
||||
#define INT_PORT_MATCH 16 // Port Match
|
||||
|
||||
#endif
|
||||
392
lib/mcs51/C8051F410.h
Normal file
392
lib/mcs51/C8051F410.h
Normal file
@@ -0,0 +1,392 @@
|
||||
/*-------------------------------------------------------------------------
|
||||
C8051F410.h - Register Declarations for the SiLabs C8051F41x
|
||||
Processor Range
|
||||
|
||||
Copyright (C) 2006, Maarten Brock, sourceforge.brock@dse.nl
|
||||
|
||||
This library is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the
|
||||
Free Software Foundation; either version 2, or (at your option) any
|
||||
later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this library; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
|
||||
MA 02110-1301, USA.
|
||||
|
||||
As a special exception, if you link this library with other files,
|
||||
some of which are compiled with SDCC, to produce an executable,
|
||||
this library does not by itself cause the resulting executable to
|
||||
be covered by the GNU General Public License. This exception does
|
||||
not however invalidate any other reasons why the executable file
|
||||
might be covered by the GNU General Public License.
|
||||
-------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef C8051F410_H
|
||||
#define C8051F410_H
|
||||
|
||||
|
||||
/* BYTE Registers */
|
||||
|
||||
__sfr __at (0x80) P0 ; /* PORT 0 */
|
||||
__sfr __at (0x81) SP ; /* STACK POINTER */
|
||||
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
|
||||
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
|
||||
__sfr __at (0x84) CRC0CN ; /* CRC 0 CONTROL */
|
||||
__sfr __at (0x85) CRC0IN ; /* CRC 0 DATA INPUT */
|
||||
__sfr __at (0x86) CRC0DAT ; /* CRC 0 DATA OUTPUT */
|
||||
__sfr __at (0x87) PCON ; /* POWER CONTROL */
|
||||
__sfr __at (0x88) TCON ; /* TIMER CONTROL */
|
||||
__sfr __at (0x89) TMOD ; /* TIMER MODE */
|
||||
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
|
||||
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
|
||||
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
|
||||
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
|
||||
__sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
|
||||
__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
|
||||
__sfr __at (0x90) P1 ; /* PORT 1 */
|
||||
__sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */
|
||||
__sfr __at (0x92) TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at (0x93) TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */
|
||||
__sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */
|
||||
__sfr __at (0x96) IDA0L ; /* CURRENT MODE DAC 0 - LOW BYTE */
|
||||
__sfr __at (0x97) IDA0H ; /* CURRENT MODE DAC 0 - HIGH BYTE */
|
||||
__sfr __at (0x98) SCON ; /* SERIAL PORT CONTROL */
|
||||
__sfr __at (0x98) SCON0 ; /* SERIAL PORT CONTROL */
|
||||
__sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
|
||||
__sfr __at (0x99) SBUF0 ; /* SERIAL PORT BUFFER */
|
||||
__sfr __at (0x9A) CPT1CN ; /* COMPARATOR 1 CONTROL */
|
||||
__sfr __at (0x9B) CPT0CN ; /* COMPARATOR 0 CONTROL */
|
||||
__sfr __at (0x9C) CPT1MD ; /* COMPARATOR 1 MODE SELECTION */
|
||||
__sfr __at (0x9D) CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
|
||||
__sfr __at (0x9E) CPT1MX ; /* COMPARATOR 1 MUX SELECTION */
|
||||
__sfr __at (0x9F) CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
|
||||
__sfr __at (0xA0) P2 ; /* PORT 2 */
|
||||
__sfr __at (0xA1) SPI0CFG ; /* SPI0 CONFIGURATION */
|
||||
__sfr __at (0xA2) SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */
|
||||
__sfr __at (0xA3) SPI0DAT ; /* SPI0 DATA */
|
||||
__sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA5) P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
|
||||
__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
|
||||
__sfr __at (0xA9) CLKSEL ; /* SYSTEM CLOCK SELECT */
|
||||
__sfr __at (0xAA) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
|
||||
__sfr __at (0xAA) _XPAGE ; /* XDATA/PDATA PAGE */
|
||||
__sfr __at (0xAB) CLKMUL ; /* CLOCK MULTIPLIER */
|
||||
__sfr __at (0xAC) RTC0ADR ; /* SMARTCLOCK ADDRESS */
|
||||
__sfr __at (0xAD) RTC0DAT ; /* SMARTCLOCK DATA */
|
||||
__sfr __at (0xAE) RTC0KEY ; /* SMARTCLOCK LOCK AND KEY */
|
||||
__sfr __at (0xAF) ONESHOT ; /* FLASH ONESHOT PERIOD */
|
||||
__sfr __at (0xB0) P0ODEN ; /* PORT 0 OVERDRIVE */
|
||||
__sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
|
||||
__sfr __at (0xB3) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
|
||||
__sfr __at (0xB5) IDA1CN ; /* CURRENT MODE DAC 1 - CONTROL */
|
||||
__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
|
||||
__sfr __at (0xB7) FLKEY ; /* FLASH ACESS LIMIT */
|
||||
__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
|
||||
__sfr __at (0xB9) IDA0CN ; /* CURRENT MODE DAC 0 - CONTROL */
|
||||
__sfr __at (0xBA) ADC0TK ; /* ADC 0 TRACKING MODE SELECT */
|
||||
__sfr __at (0xBB) ADC0MX ; /* ADC 0 CHANNEL SELECT */
|
||||
__sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */
|
||||
__sfr __at (0xBD) ADC0L ; /* ADC 0 DATA WORD LSB */
|
||||
__sfr __at (0xBE) ADC0H ; /* ADC 0 DATA WORD MSB */
|
||||
__sfr __at (0xBF) P1MASK ; /* PORT 1 MASK */
|
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__sfr __at (0xC0) SMB0CN ; /* SMBUS CONTROL */
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||||
__sfr __at (0xC1) SMB0CF ; /* SMBUS CONFIGURATION */
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||||
__sfr __at (0xC2) SMB0DAT ; /* SMBUS DATA */
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||||
__sfr __at (0xC3) ADC0GTL ; /* ADC 0 GREATER-THAN LOW BYTE */
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||||
__sfr __at (0xC4) ADC0GTH ; /* ADC 0 GREATER-THAN HIGH BYTE */
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||||
__sfr __at (0xC5) ADC0LTL ; /* ADC 0 LESS-THAN LOW BYTE */
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||||
__sfr __at (0xC6) ADC0LTH ; /* ADC 0 LESS-THAN HIGH BYTE */
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||||
__sfr __at (0xC7) P0MASK ; /* PORT 0 MASK */
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||||
__sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
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||||
__sfr __at (0xC8) TMR2CN ; /* TIMER 2 CONTROL */
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||||
__sfr __at (0xC9) REG0CN ; /* VOLTAGE REGULATOR CONTROL */
|
||||
__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
|
||||
__sfr __at (0xCA) TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
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||||
__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
|
||||
__sfr __at (0xCB) TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
|
||||