feat(pcb): relays layout
This commit is contained in:
1
hardware/pcb/.history
Submodule
1
hardware/pcb/.history
Submodule
Submodule hardware/pcb/.history added at b3c40bcfbd
File diff suppressed because it is too large
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@@ -4,7 +4,9 @@
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"active_layer_preset": "",
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"auto_track_width": true,
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"hidden_netclasses": [],
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"hidden_nets": [],
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"hidden_nets": [
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"GND"
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],
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"high_contrast_mode": 0,
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"net_color_mode": 1,
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"opacity": {
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@@ -15,6 +17,7 @@
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"vias": 1.0,
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"zones": 0.6
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},
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"prototype_zone_fills": false,
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"selection_filter": {
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"dimensions": true,
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"footprints": true,
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@@ -107,6 +110,7 @@
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"filter_text": "",
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"group_by_constraint": false,
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"group_by_netclass": false,
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"show_time_domain_details": false,
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"show_unconnected_nets": false,
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"show_zero_pad_nets": false,
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"sort_ascending": true,
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@@ -117,6 +121,7 @@
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"files": []
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},
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"schematic": {
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"hierarchy_collapsed": [],
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"selection_filter": {
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"graphics": true,
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"images": true,
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@@ -124,6 +129,7 @@
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"lockedItems": false,
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"otherItems": true,
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"pins": true,
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"ruleAreas": true,
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"symbols": true,
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"text": true,
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"wires": true
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@@ -3,6 +3,8 @@
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"3dviewports": [],
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"design_settings": {
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"defaults": {
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"apply_defaults_to_fp_barcodes": false,
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"apply_defaults_to_fp_dimensions": false,
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"apply_defaults_to_fp_fields": false,
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"apply_defaults_to_fp_shapes": false,
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"apply_defaults_to_fp_text": false,
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@@ -77,6 +79,7 @@
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"extra_footprint": "warning",
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"footprint": "error",
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"footprint_filters_mismatch": "ignore",
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"footprint_symbol_field_mismatch": "warning",
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"footprint_symbol_mismatch": "warning",
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"footprint_type_mismatch": "ignore",
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"hole_clearance": "error",
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@@ -94,6 +97,7 @@
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"mirrored_text_on_front_layer": "warning",
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"missing_courtyard": "ignore",
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"missing_footprint": "warning",
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"missing_tuning_profile": "warning",
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"net_conflict": "warning",
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"nonmirrored_text_on_back_layer": "warning",
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"npth_inside_courtyard": "ignore",
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@@ -107,14 +111,18 @@
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"solder_mask_bridge": "error",
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"starved_thermal": "error",
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"text_height": "warning",
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"text_on_edge_cuts": "error",
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"text_thickness": "warning",
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"through_hole_pad_without_hole": "error",
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"too_many_vias": "error",
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"track_angle": "error",
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"track_dangling": "warning",
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"track_not_centered_on_via": "ignore",
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"track_on_post_machined_layer": "error",
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"track_segment_length": "error",
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"track_width": "error",
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"tracks_crossing": "error",
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"tuning_profile_track_geometries": "ignore",
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"unconnected_items": "error",
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"unresolved_variable": "error",
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"via_dangling": "warning",
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@@ -227,17 +235,28 @@
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"zones_allow_external_fillets": false
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},
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"ipc2581": {
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"bom_rev": "",
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"dist": "",
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"distpn": "",
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"internal_id": "",
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"mfg": "",
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"mpn": ""
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"mpn": "",
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"sch_revision": "1.0.0"
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},
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"layer_pairs": [],
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"layer_presets": [],
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"viewports": []
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},
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"boards": [],
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"component_class_settings": {
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"assignments": [],
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"meta": {
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"version": 0
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},
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"sheet_component_classes": {
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"enabled": false
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}
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},
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"cvpcb": {
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"equivalence_files": []
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},
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@@ -427,11 +446,14 @@
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"duplicate_sheet_names": "error",
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"endpoint_off_grid": "warning",
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"extra_units": "error",
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"field_name_whitespace": "warning",
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"footprint_filter": "ignore",
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"footprint_link_issues": "warning",
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"four_way_junction": "ignore",
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"global_label_dangling": "warning",
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"ground_pin_not_ground": "warning",
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"hier_label_mismatch": "error",
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"isolated_pin_label": "warning",
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"label_dangling": "error",
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"label_multiple_wires": "warning",
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"lib_symbol_issues": "warning",
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@@ -454,6 +476,7 @@
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"similar_power": "warning",
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"simulation_model_issue": "ignore",
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"single_global_label": "ignore",
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"stacked_pin_name": "warning",
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"unannotated": "error",
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"unconnected_wire_endpoint": "warning",
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"undefined_netclass": "error",
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@@ -492,6 +515,7 @@
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"priority": 2147483647,
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.254,
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"tuning_profile": "",
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"via_diameter": 0.6,
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"via_drill": 0.3,
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"wire_width": 6
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@@ -501,25 +525,28 @@
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 2,
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 8.0
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"track_width": 8.0,
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"tuning_profile": ""
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},
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{
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"name": "Power Low",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 0,
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 2.54
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"track_width": 2.54,
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"tuning_profile": ""
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},
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{
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"name": "Power Out",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 1,
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 6.0
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"track_width": 6.0,
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"tuning_profile": ""
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}
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],
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"meta": {
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"version": 4
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"version": 5
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},
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"net_colors": null,
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"netclass_assignments": null,
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@@ -566,6 +593,10 @@
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},
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"schematic": {
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"annotate_start_num": 0,
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"annotation": {
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"method": 0,
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"sort_order": 0
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},
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"bom_export_filename": "${PROJECTNAME}.csv",
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"bom_fmt_presets": [],
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"bom_fmt_settings": {
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@@ -637,6 +668,7 @@
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"sort_asc": true,
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"sort_field": "位号"
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},
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"bus_aliases": {},
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"connection_grid_size": 50.0,
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"drawing": {
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"dashed_lines_dash_length_ratio": 12.0,
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@@ -644,6 +676,7 @@
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"default_line_thickness": 6.0,
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"default_text_size": 50.0,
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"field_names": [],
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"hop_over_size_choice": 0,
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"intersheets_ref_own_page": false,
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"intersheets_ref_prefix": "",
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"intersheets_ref_short": false,
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@@ -667,6 +700,7 @@
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"net_format_name": "",
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"page_layout_descr_file": "",
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"plot_directory": "",
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"reuse_designators": true,
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"space_save_all_events": true,
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"spice_current_sheet_as_root": false,
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"spice_external_command": "spice \"%I\"",
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@@ -675,13 +709,28 @@
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"spice_save_all_dissipations": false,
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"spice_save_all_voltages": false,
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"subpart_first_id": 65,
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"subpart_id_separator": 0
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"subpart_id_separator": 0,
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"top_level_sheets": [
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{
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"filename": "HeliosDAONE.kicad_sch",
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"name": "HeliosDAONE",
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"uuid": "ef4a6f87-87d3-400e-b11f-0c7519b83474"
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}
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],
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"used_designators": "NT1,J4",
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"variants": []
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},
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"sheets": [
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[
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"ef4a6f87-87d3-400e-b11f-0c7519b83474",
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"Root"
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"HeliosDAONE"
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]
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],
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"text_variables": {}
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"text_variables": {},
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"tuning_profiles": {
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"meta": {
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"version": 0
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},
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"tuning_profiles_impedance_geometric": []
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}
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}
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@@ -1,4 +1,5 @@
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(design_block_lib_table
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(version 7)
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(lib (name "converted.3dmodels")(type "KiCad")(uri "${KIPRJMOD}/library/converted.3dmodels")(options "")(descr ""))
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(version 7)
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(lib (name "converted.3dmodels") (type "KiCad") (uri "${KIPRJMOD}/library/converted.3dmodels") (options "") (descr ""))
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(lib (name "RayineComponents.3dmodels") (type "KiCad") (uri "${KIPRJMOD}/library/RayineComponents.3dmodels") (options "") (descr ""))
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)
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182883
hardware/pcb/fp-info-cache
182883
hardware/pcb/fp-info-cache
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@@ -1,4 +1,5 @@
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(fp_lib_table
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(version 7)
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(lib (name "converted")(type "KiCad")(uri "${KIPRJMOD}/library/converted.pretty")(options "")(descr ""))
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(version 7)
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(lib (name "converted") (type "KiCad") (uri "${KIPRJMOD}/library/converted.pretty") (options "") (descr ""))
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(lib (name "RayineComponents") (type "KiCad") (uri "${KIPRJMOD}/library/RayineComponents.pretty") (options "") (descr ""))
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)
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22086
hardware/pcb/library/RayineComponents.3dmodels/IM1281B.step
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22086
hardware/pcb/library/RayineComponents.3dmodels/IM1281B.step
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16500
hardware/pcb/library/RayineComponents.3dmodels/JQC-3FF-005-1Z.step
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hardware/pcb/library/RayineComponents.3dmodels/JQC-3FF-005-1Z.step
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27873
hardware/pcb/library/RayineComponents.3dmodels/RFID-RC522.STEP
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27873
hardware/pcb/library/RayineComponents.3dmodels/RFID-RC522.STEP
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172931
hardware/pcb/library/RayineComponents.3dmodels/STM32F103C8T6 Blue Pill.step
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172931
hardware/pcb/library/RayineComponents.3dmodels/STM32F103C8T6 Blue Pill.step
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17426
hardware/pcb/library/RayineComponents.3dmodels/TS-1187A-B-A-B.step
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17426
hardware/pcb/library/RayineComponents.3dmodels/TS-1187A-B-A-B.step
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44805
hardware/pcb/library/RayineComponents.bak
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44805
hardware/pcb/library/RayineComponents.bak
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@@ -1,4 +1,5 @@
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(sym_lib_table
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(version 7)
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(lib (name "converted")(type "KiCad")(uri "${KIPRJMOD}/library/converted.kicad_sym")(options "")(descr ""))
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(version 7)
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(lib (name "converted") (type "KiCad") (uri "${KIPRJMOD}/library/converted.kicad_sym") (options "") (descr ""))
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(lib (name "RayineComponents") (type "KiCad") (uri "${KIPRJMOD}/library/RayineComponents.kicad_sym") (options "") (descr ""))
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)
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