486 lines
12 KiB
C
486 lines
12 KiB
C
/*-------------------------------------------------------------------------
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P89LPC925.h - Register Declarations for NXP P89LPC924 and P89LPC925
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(Based on datasheet Rev. 03 — 15 December 2004)
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Copyright (C) 2007, Jesus Calvino-Fraga / jesusc at ece.ubc.ca
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This library is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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Free Software Foundation; either version 2, or (at your option) any
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later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this library; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
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MA 02110-1301, USA.
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As a special exception, if you link this library with other files,
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some of which are compiled with SDCC, to produce an executable,
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this library does not by itself cause the resulting executable to
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be covered by the GNU General Public License. This exception does
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not however invalidate any other reasons why the executable file
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might be covered by the GNU General Public License.
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-------------------------------------------------------------------------*/
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#ifndef REG_P89LPC925_H
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#define REG_P89LPC925_H
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#include <compiler.h>
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SFR(ACC, 0xE0); // Accumulator
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SBIT(ACC_7, 0xE0, 7);
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SBIT(ACC_6, 0xE0, 6);
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SBIT(ACC_5, 0xE0, 5);
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SBIT(ACC_4, 0xE0, 4);
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SBIT(ACC_3, 0xE0, 3);
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SBIT(ACC_2, 0xE0, 2);
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SBIT(ACC_1, 0xE0, 1);
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SBIT(ACC_0, 0xE0, 0);
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SFR(ADCON1, 0x97); // A/D control register 1
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#define ENBI1 0x80
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#define ENADCI1 0x40
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#define TMM1 0x20
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#define EDGE1 0x10
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#define ADCI1 0x08
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#define ENADC1 0x04
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#define ADCS11 0x02
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#define ADCS10 0x01
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SFR(ADINS, 0xA3); // A/D input select
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#define ADI13 0x80
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#define ADI12 0x40
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#define ADI11 0x20
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#define ADI10 0x10
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SFR(ADMODA, 0xC0); // A/D mode register A
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#define BNDI1 0x80
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#define BURST1 0x40
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#define SCC1 0x20
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#define SCAN1 0x10
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SFR(ADMODB, 0xA1); // A/D mode register B
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#define CLK2 0x80
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#define CLK1 0x40
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#define CLK0 0x20
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#define ENDAC1 0x08
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#define BSA1 0x02
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SFR(AD1BH, 0xC4); // A/D_1 boundary high register
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SFR(AD1BL, 0xBC); // A/D_1 boundary low register
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SFR(AD1DAT0, 0xD5); // A/D_1 data register 0
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SFR(AD1DAT1, 0xD6); // A/D_1 data register 1
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SFR(AD1DAT2, 0xD7); // A/D_1 data register 2
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SFR(AD1DAT3, 0xF5); // A/D_1 data register 3
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SFR(AUXR1, 0xA2); // Auxiliary function register
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#define CLKLP 0x80
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#define EBRR 0x40
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#define ENT1 0x20
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#define ENT0 0x10
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#define SRST 0x08
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#define DPS 0x01
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SFR(B, 0xF0); // B register
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SBIT(B_7, 0xF0, 7);
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SBIT(B_6, 0xF0, 6);
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SBIT(B_5, 0xF0, 5);
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SBIT(B_4, 0xF0, 4);
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SBIT(B_3, 0xF0, 3);
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SBIT(B_2, 0xF0, 2);
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SBIT(B_1, 0xF0, 1);
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SBIT(B_0, 0xF0, 0);
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SFR(BRGR0, 0xBE); // Baud rate generator rate LOW
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SFR(BRGR1, 0xBF); // Baud rate generator rate HIGH
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SFR(BRGCON, 0xBD); // Baud rate generator control
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#define SBRGS 0x02
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#define BRGEN 0x01
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SFR(CMP1, 0xAC); // Comparator1 control register
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#define CE1 0x20
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#define CP1 0x10
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#define CN1 0x08
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#define OE1 0x04
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#define CO1 0x02
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#define CMF1 0x01
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SFR(CMP2, 0xAD); // Comparator2 control register
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#define CE2 0x20
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#define CP2 0x10
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#define CN2 0x08
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#define OE2 0x04
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#define CO2 0x02
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#define CMF2 0x01
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SFR(DIVM, 0x95); // CPU clock divide-by-M control
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SFR(DPH, 0x83); // Data pointer HIGH
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SFR(DPL, 0x82); // Data pointer LOW
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SFR(FMADRH, 0xE7); // Program Flash address HIGH
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SFR(FMADRL, 0xE6); // Program Flash address LOW
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SFR(FMCON, 0xE4); // Program Flash control (Read)
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#define BUSY 0x80
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#define HVA 0x08
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#define HVE 0x04
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#define SV 0x02
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#define OI 0x01
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SFR(FMCON, 0xE4); // Program Flash control (Write)
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#define FMCMD_7 0x80
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#define FMCMD_6 0x40
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#define FMCMD_5 0x20
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#define FMCMD_4 0x10
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#define FMCMD_3 0x08
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#define FMCMD_2 0x04
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#define FMCMD_1 0x02
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#define FMCMD_0 0x01
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SFR(FMDATA, 0xE5); // Program Flash data
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SFR(I2ADR, 0xDB); // I2C slave address register
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#define I2ADR_6 0x80
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#define I2ADR_5 0x40
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#define I2ADR_4 0x20
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#define I2ADR_3 0x10
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#define I2ADR_2 0x08
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#define I2ADR_1 0x04
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#define I2ADR_0 0x02
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#define GC 0x01
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SFR(I2CON, 0xD8); // I2C control register
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SBIT(I2EN, 0xD8, 6);
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SBIT(STA, 0xD8, 5);
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SBIT(STO, 0xD8, 4);
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SBIT(SI, 0xD8, 3);
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SBIT(AA, 0xD8, 2);
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SBIT(CRSEL, 0xD8, 0);
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SFR(I2DAT, 0xDA); // I2C data register
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SFR(I2SCLH, 0xDD); // Serial clock generator/SCL duty cycle register HIGH
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SFR(I2SCLL, 0xDC); // Serial clock generator/SCL duty cycle register LOW
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SFR(I2STAT, 0xD9); // I2C status register
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#define STA_4 0x80
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#define STA_3 0x40
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#define STA_2 0x20
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#define STA_1 0x10
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#define STA_0 0x08
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SFR(IEN0, 0xA8); // Interrupt enable 0
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SBIT(EA, 0xA8, 7);
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SBIT(EWDRT, 0xA8, 6);
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SBIT(EBO, 0xA8, 5);
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SBIT(ES, 0xA8, 4);
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SBIT(ESR, 0xA8, 4);
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SBIT(ET1, 0xA8, 3);
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SBIT(EX1, 0xA8, 2);
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SBIT(ET0, 0xA8, 1);
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SBIT(EX0, 0xA8, 0);
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SFR(IEN1, 0xE8); // Interrupt enable 1
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SBIT(EAD, 0xE8, 7);
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SBIT(EST, 0xE8, 6);
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SBIT(EC, 0xE8, 2);
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SBIT(EKBI, 0xE8, 1);
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SBIT(EI2C, 0xE8, 0);
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SFR(IP0, 0xB8); // Interrupt priority 0
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SBIT(PWDRT, 0xB8, 6);
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SBIT(PBO, 0xB8, 5);
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SBIT(PS, 0xB8, 4);
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SBIT(PSR, 0xB8, 4);
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SBIT(PT1, 0xB8, 3);
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SBIT(PX1, 0xB8, 2);
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SBIT(PT0, 0xB8, 1);
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SBIT(PX0, 0xB8, 0);
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SFR(IP0H, 0xB7); // Interrupt priority 0 HIGH
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#define PWDRTH 0x40
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#define PBOH 0x20
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#define PSH 0x10
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#define PSRH 0x10
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#define PT1H 0x08
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#define PX1H 0x04
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#define PT0H 0x02
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#define PX0H 0x01
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SFR(IP1, 0xF8); // Interrupt priority 1
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SBIT(PAD, 0xF8, 7);
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SBIT(PST, 0xF8, 6);
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SBIT(PC, 0xF8, 2);
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SBIT(PKBI, 0xF8, 1);
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SBIT(PI2C, 0xF8, 0);
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SFR(IP1H, 0xF7); // Interrupt priority 1 HIGH
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#define PADH 0x80
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#define PSTH 0x40
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#define PCH 0x04
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#define PKBIH 0x02
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#define PI2CH 0x01
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SFR(KBCON, 0x94); // Keypad control register
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#define PATN_SEL 0x02 //Pattern Matching Polarity selection
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#define KBIF 0x01 // Keypad Interrupt Flag
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SFR(KBMASK, 0x86); // Keypad interrupt register mask
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SFR(KBPATN, 0x93); // Keypad pattern register
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SFR(P0, 0x80); // Port 0
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SBIT(P0_7, 0x80, 7);
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SBIT(P0_6, 0x80, 6);
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SBIT(P0_5, 0x80, 5);
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SBIT(P0_4, 0x80, 4);
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SBIT(P0_3, 0x80, 3);
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SBIT(P0_2, 0x80, 2);
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SBIT(P0_1, 0x80, 1);
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SBIT(P0_0, 0x80, 0);
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//P0 alternate pin functions
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SBIT(T1, 0x80, 7);
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SBIT(CMP_1, 0x80, 6); //Should be CMP1 but there is SFR with that name
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SBIT(CMPREF, 0x80, 5);
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SBIT(CIN1A, 0x80, 4);
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SBIT(CIN1B, 0x80, 3);
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SBIT(CIN2A, 0x80, 2);
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SBIT(CIN2B, 0x80, 1);
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SBIT(CMP_2, 0x80, 0); //Should be CMP2 but there is SFR with that name
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//More P0 alternate pin functions
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SBIT(KB7, 0x80, 7);
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SBIT(KB6, 0x80, 6);
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SBIT(KB5, 0x80, 5);
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SBIT(KB4, 0x80, 4);
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SBIT(KB3, 0x80, 3);
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SBIT(KB2, 0x80, 2);
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SBIT(KB1, 0x80, 1);
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SBIT(KB0, 0x80, 0);
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SFR(P1, 0x90); // Port 1
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SBIT(P1_7, 0x90, 7);
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SBIT(P1_6, 0x90, 6);
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SBIT(P1_5, 0x90, 5);
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SBIT(P1_4, 0x90, 4);
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SBIT(P1_3, 0x90, 3);
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SBIT(P1_2, 0x90, 2);
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SBIT(P1_1, 0x90, 1);
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SBIT(P1_0, 0x90, 0);
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//P1 alternate pin functions
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SBIT(RST, 0x90, 5);
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SBIT(INT1, 0x90, 4);
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SBIT(INT0, 0x90, 3);
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SBIT(SDA, 0x90, 3);
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SBIT(T0, 0x90, 2);
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SBIT(SCL, 0x90, 2);
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SBIT(RXD, 0x90, 1);
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SBIT(TXD, 0x90, 0);
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SFR(P3, 0xB0); // Port 3
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SBIT(P3_1, 0xB0, 1);
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SBIT(P3_0, 0xB0, 0);
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SBIT(XTAL1, 0xB0, 1);
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SBIT(XTAL2, 0xB0, 0);
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SFR(P0M1, 0x84); // Port0 output mode1
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#define P0M1_7 0x80
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#define P0M1_6 0x40
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#define P0M1_5 0x20
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#define P0M1_4 0x10
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#define P0M1_3 0x08
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#define P0M1_2 0x04
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#define P0M1_1 0x02
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#define P0M1_0 0x01
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SFR(P0M2, 0x85); // Port0 output mode2
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#define P0M2_7 0x80
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#define P0M2_6 0x40
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#define P0M2_5 0x20
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#define P0M2_4 0x10
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#define P0M2_3 0x08
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#define P0M2_2 0x04
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#define P0M2_1 0x02
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#define P0M2_0 0x01
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SFR(P1M1, 0x91); // Port1 output mode1
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#define P1M1_7 0x80
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#define P1M1_6 0x40
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#define P1M1_4 0x10
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#define P1M1_3 0x08
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#define P1M1_2 0x04
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#define P1M1_1 0x02
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#define P1M1_0 0x01
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SFR(P1M2, 0x92); // Port1 output mode2
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#define P1M2_7 0x80
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#define P1M2_6 0x40
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#define P1M2_4 0x10
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#define P1M2_3 0x08
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#define P1M2_2 0x04
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#define P1M2_1 0x02
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#define P1M2_0 0x01
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SFR(P3M1, 0xB1); // Port3 output mode1
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#define P3M1_1 0x02
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#define P3M1_0 0x01
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SFR(P3M2, 0xB2); // Port3 output mode2
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#define P3M2_1 0x02
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#define P3M2_0 0x01
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SFR(PCON, 0x87); // Power control register
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#define SMOD1 0x80
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#define SMOD0 0x40
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#define BOPD 0x20
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#define BOI 0x10
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#define GF1 0x08
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#define GF0 0x04
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#define PMOD1 0x02
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#define PMOD0 0x01
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SFR(PCONA, 0xB5); // Power control register A
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#define RTCPD 0x80
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#define VCPD 0x20
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#define ADPD 0x10
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#define I2PD 0x08
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#define SPD 0x02
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SFR(PSW, 0xD0); // Program status word
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SBIT(CY, 0xD0, 7);
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SBIT(AC, 0xD0, 6);
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SBIT(F0, 0xD0, 5);
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SBIT(RS1, 0xD0, 4);
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SBIT(RS0, 0xD0, 3);
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SBIT(OV, 0xD0, 2);
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SBIT(F1, 0xD0, 1);
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SBIT(P, 0xD0, 0);
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SFR(PT0AD, 0xF6); // Port0 digital input disable
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#define PT0AD_5 0x20
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#define PT0AD_4 0x10
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#define PT0AD_3 0x08
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#define PT0AD_2 0x04
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#define PT0AD_1 0x02
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SFR(RSTSRC, 0xDF); // Reset source register
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#define BOF 0x20
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#define POF 0x10
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#define R_BK 0x08
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#define R_WD 0x04
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#define R_SF 0x02
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#define R_EX 0x01
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SFR(RTCCON, 0xD1); // Real-time clock control
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#define RTCF 0x80
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#define RTCS1 0x40
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#define RTCS0 0x20
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#define ERTC 0x02
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#define RTCEN 0x01
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SFR(RTCH, 0xD2); // Real-time clock register HIGH
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SFR(RTCL, 0xD3); // Real-time clock register LOW
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SFR(SADDR, 0xA9); // Serial port address register
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SFR(SADEN, 0xB9); // Serial port address enable
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SFR(SBUF, 0x99); // Serial Port data buffer register
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SFR(SCON, 0x98); // Serial port control
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SBIT(FE, 0x98, 7);
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SBIT(SM0, 0x98, 7);
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SBIT(SM1, 0x98, 6);
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SBIT(SM2, 0x98, 5);
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SBIT(REN, 0x98, 4);
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SBIT(TB8, 0x98, 3);
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SBIT(RB8, 0x98, 2);
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SBIT(TI, 0x98, 1);
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SBIT(RI, 0x98, 0);
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SFR(SSTAT, 0xBA); // Serial port extended status register
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#define DBMOD 0x80
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#define INTLO 0x40
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#define CIDIS 0x20
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#define DBISEL 0x10
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#define FE 0x08
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#define BR 0x04
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#define OE 0x02
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#define STINT 0x01
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SFR(SP, 0x81); // Stack pointer
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SFR(TAMOD, 0x8F); // Timer0 and 1 auxiliary mode
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#define T1M2 0x10
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#define T0M2 0x01
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SFR(TCON, 0x88); // Timer0 and 1 control
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SBIT(TF1, 0x88, 7);
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SBIT(TR1, 0x88, 6);
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SBIT(TF0, 0x88, 5);
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SBIT(TR0, 0x88, 4);
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SBIT(IE1, 0x88, 3);
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SBIT(IT1, 0x88, 2);
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SBIT(IE0, 0x88, 1);
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SBIT(IT0, 0x88, 0);
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SFR(TH0, 0x8C); // Timer0 HIGH
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SFR(TH1, 0x8D); // Timer 1 HIGH
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SFR(TL0, 0x8A); // Timer 0 LOW
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SFR(TL1, 0x8B); // Timer 1 LOW
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SFR(TMOD, 0x89); // Timer0 and 1 mode
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#define T1GATE 0x80
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#define T1C_T 0x40
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#define T1M1 0x20
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#define T1M0 0x10
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#define T0GATE 0x08
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#define T0C_T 0x04
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#define T0M1 0x02
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#define T0M0 0x01
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SFR(TRIM, 0x96); // Internal oscillator trim register
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#define RCCLK 0x80
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#define ENCLK 0x40
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#define TRIM_5 0x20
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#define TRIM_4 0x10
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#define TRIM_3 0x08
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#define TRIM_2 0x04
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#define TRIM_1 0x02
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#define TRIM_0 0x01
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SFR(WDCON, 0xA7); // Watchdog control register
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#define PRE2 0x80 //Watchdog Prescaler Tap Select bit 2
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#define PRE1 0x40 //Watchdog Prescaler Tap Select bit 1
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#define PRE0 0x20 //Watchdog Prescaler Tap Select bit 0
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#define WDRUN 0x04 //Watchdog Run Control
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#define WDTOF 0x02 //Watchdog Timer Time-Out Flag
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#define WDCLK 0x01 //Watchdog input clock select
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SFR(WDL, 0xC1); // Watchdog load
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SFR(WFEED1, 0xC2); // Watchdog feed 1
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SFR(WFEED2, 0xC3); // Watchdog feed 2
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#endif /*REG_P89LPC925_H*/
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