404 lines
11 KiB
C
404 lines
11 KiB
C
/*-------------------------------------------------------------------------
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XC866.h - register Declarations for the Infineon XC866
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Copyright (C) 2005, Llewellyn van Zyl <eduprep AT myconnection.co.za>
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This library is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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Free Software Foundation; either version 2, or (at your option) any
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later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this library; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
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MA 02110-1301, USA.
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As a special exception, if you link this library with other files,
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some of which are compiled with SDCC, to produce an executable,
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this library does not by itself cause the resulting executable to
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be covered by the GNU General Public License. This exception does
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not however invalidate any other reasons why the executable file
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might be covered by the GNU General Public License.
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-------------------------------------------------------------------------*/
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#ifndef XC866_H
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#define XC866_H
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// SFR byte definitions
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__sfr __at (0xE0) A;
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__sfr __at (0xCA) ADC_CHCTR0;
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__sfr __at (0xCB) ADC_CHCTR1;
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__sfr __at (0xCC) ADC_CHCTR2;
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__sfr __at (0xCD) ADC_CHCTR3;
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__sfr __at (0xCE) ADC_CHCTR4;
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__sfr __at (0xCF) ADC_CHCTR5;
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__sfr __at (0xD2) ADC_CHCTR6;
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__sfr __at (0xD3) ADC_CHCTR7;
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__sfr __at (0xCB) ADC_CHINCR;
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__sfr __at (0xCA) ADC_CHINFR;
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__sfr __at (0xCD) ADC_CHINPR;
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__sfr __at (0xCC) ADC_CHINSR;
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__sfr __at (0xCA) ADC_CRCR1;
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__sfr __at (0xCC) ADC_CRMR1;
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__sfr __at (0xCB) ADC_CRPR1;
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__sfr __at (0xCF) ADC_ETRCR;
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__sfr __at (0xCF) ADC_EVINCR;
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__sfr __at (0xCE) ADC_EVINFR;
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__sfr __at (0xD3) ADC_EVINPR;
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__sfr __at (0xD2) ADC_EVINSR;
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__sfr __at (0xCA) ADC_GLOBCTR;
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__sfr __at (0xCB) ADC_GLOBSTR;
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__sfr __at (0xCE) ADC_INPCR0;
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__sfr __at (0xCD) ADC_LCBR;
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__sfr __at (0xD1) ADC_PAGE;
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__sfr __at (0xCC) ADC_PRAR;
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__sfr __at (0xCF) ADC_Q0R0;
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__sfr __at (0xD2) ADC_QBUR0;
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__sfr __at (0xD2) ADC_QINR0;
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__sfr __at (0xCD) ADC_QMR0;
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__sfr __at (0xCE) ADC_QSR0;
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__sfr __at (0xCA) ADC_RCR0;
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__sfr __at (0xCB) ADC_RCR1;
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__sfr __at (0xCC) ADC_RCR2;
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__sfr __at (0xCD) ADC_RCR3;
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__sfr __at (0xCB) ADC_RESR0H;
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__sfr __at (0xCA) ADC_RESR0L;
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__sfr __at (0xCD) ADC_RESR1H;
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__sfr __at (0xCC) ADC_RESR1L;
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__sfr __at (0xCF) ADC_RESR2H;
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__sfr __at (0xCE) ADC_RESR2L;
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__sfr __at (0xD3) ADC_RESR3H;
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__sfr __at (0xD2) ADC_RESR3L;
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__sfr __at (0xCB) ADC_RESRA0H;
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__sfr __at (0xCA) ADC_RESRA0L;
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__sfr __at (0xCD) ADC_RESRA1H;
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__sfr __at (0xCC) ADC_RESRA1L;
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__sfr __at (0xCF) ADC_RESRA2H;
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__sfr __at (0xCE) ADC_RESRA2L;
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__sfr __at (0xD3) ADC_RESRA3H;
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__sfr __at (0xD2) ADC_RESRA3L;
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__sfr __at (0xCE) ADC_VFCR;
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__sfr __at (0xF0) B;
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__sfr __at (0xBD) BCON;
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__sfr __at (0xBE) BG;
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__sfr __at (0xFB) CCU6_CC60RH;
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__sfr __at (0xFA) CCU6_CC60RL;
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__sfr __at (0xFB) CCU6_CC60SRH;
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__sfr __at (0xFA) CCU6_CC60SRL;
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__sfr __at (0xFD) CCU6_CC61RH;
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__sfr __at (0xFC) CCU6_CC61RL;
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__sfr __at (0xFD) CCU6_CC61SRH;
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__sfr __at (0xFC) CCU6_CC61SRL;
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__sfr __at (0xFF) CCU6_CC62RH;
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__sfr __at (0xFE) CCU6_CC62RL;
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__sfr __at (0xFF) CCU6_CC62SRH;
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__sfr __at (0xFE) CCU6_CC62SRL;
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__sfr __at (0x9B) CCU6_CC63RH;
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__sfr __at (0x9A) CCU6_CC63RL;
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__sfr __at (0x9B) CCU6_CC63SRH;
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__sfr __at (0x9A) CCU6_CC63SRL;
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__sfr __at (0xA7) CCU6_CMPMODIFH;
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__sfr __at (0xA6) CCU6_CMPMODIFL;
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__sfr __at (0xFF) CCU6_CMPSTATH;
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__sfr __at (0xFE) CCU6_CMPSTATL;
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__sfr __at (0x9D) CCU6_IENH;
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__sfr __at (0x9C) CCU6_IENL;
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__sfr __at (0x9F) CCU6_INPH;
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__sfr __at (0x9E) CCU6_INPL;
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__sfr __at (0x9D) CCU6_ISH;
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__sfr __at (0x9C) CCU6_ISL;
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__sfr __at (0xA5) CCU6_ISRH;
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__sfr __at (0xA4) CCU6_ISRL;
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__sfr __at (0xA5) CCU6_ISSH;
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__sfr __at (0xA4) CCU6_ISSL;
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__sfr __at (0xA7) CCU6_MCMCTR;
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__sfr __at (0x9B) CCU6_MCMOUTH;
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__sfr __at (0x9A) CCU6_MCMOUTL;
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__sfr __at (0x9F) CCU6_MCMOUTSH;
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__sfr __at (0x9E) CCU6_MCMOUTSL;
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__sfr __at (0xFD) CCU6_MODCTRH;
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__sfr __at (0xFC) CCU6_MODCTRL;
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__sfr __at (0xA3) CCU6_PAGE;
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__sfr __at (0x9F) CCU6_PISEL0H;
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__sfr __at (0x9E) CCU6_PISEL0L;
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__sfr __at (0xA4) CCU6_PISEL2;
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__sfr __at (0xA6) CCU6_PSLR;
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__sfr __at (0xA5) CCU6_T12DTCH;
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__sfr __at (0xA4) CCU6_T12DTCL;
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__sfr __at (0xFB) CCU6_T12H;
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__sfr __at (0xFA) CCU6_T12L;
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__sfr __at (0x9B) CCU6_T12MSELH;
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__sfr __at (0x9A) CCU6_T12MSELL;
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__sfr __at (0x9D) CCU6_T12PRH;
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__sfr __at (0x9C) CCU6_T12PRL;
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__sfr __at (0xFD) CCU6_T13H;
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__sfr __at (0xFC) CCU6_T13L;
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__sfr __at (0x9F) CCU6_T13PRH;
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__sfr __at (0x9E) CCU6_T13PRL;
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__sfr __at (0xA7) CCU6_TCTR0H;
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__sfr __at (0xA6) CCU6_TCTR0L;
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__sfr __at (0xFB) CCU6_TCTR2H;
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__sfr __at (0xFA) CCU6_TCTR2L;
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__sfr __at (0x9D) CCU6_TCTR4H;
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__sfr __at (0x9C) CCU6_TCTR4L;
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__sfr __at (0xFF) CCU6_TRPCTRH;
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__sfr __at (0xFE) CCU6_TRPCTRL;
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__sfr __at (0xBA) CMCON;
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__sfr __at (0x83) DPH;
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__sfr __at (0x82) DPL;
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__sfr __at (0xA2) EO;
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__sfr __at (0xB7) EXICON0;
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__sfr __at (0xBA) EXICON1;
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__sfr __at (0xBD) FEAH;
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__sfr __at (0xBC) FEAL;
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__sfr __at (0xF7) HWBPDR;
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__sfr __at (0xF6) HWBPSR;
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__sfr __at (0xB3) ID;
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__sfr __at (0xA8) IEN0;
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__sfr __at (0xE8) IEN1;
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__sfr __at (0xB8) IP;
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__sfr __at (0xF8) IP1;
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__sfr __at (0xB9) IPH;
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__sfr __at (0xF9) IPH1;
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__sfr __at (0xB4) IRCON0;
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__sfr __at (0xB5) IRCON1;
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__sfr __at (0xF3) MMBPCR;
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__sfr __at (0xF1) MMCR;
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__sfr __at (0xE9) MMCR2;
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__sfr __at (0xF5) MMDR;
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__sfr __at (0xF4) MMICR;
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__sfr __at (0xF2) MMSR;
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__sfr __at (0xB3) MODPISEL;
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__sfr __at (0xBB) NMICON;
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__sfr __at (0xBC) NMISR;
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__sfr __at (0xB6) OSC_CON;
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__sfr __at (0x80) P0_ALTSEL0;
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__sfr __at (0x86) P0_ALTSEL1;
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__sfr __at (0x80) P0_DATA;
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__sfr __at (0x86) P0_DIR;
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__sfr __at (0x80) P0_OD;
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__sfr __at (0x86) P0_PUDEN;
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__sfr __at (0x80) P0_PUDSEL;
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__sfr __at (0x90) P1_ALTSEL0;
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__sfr __at (0x91) P1_ALTSEL1;
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__sfr __at (0x90) P1_DATA;
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__sfr __at (0x91) P1_DIR;
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__sfr __at (0x90) P1_OD;
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__sfr __at (0x91) P1_PUDEN;
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__sfr __at (0x90) P1_PUDSEL;
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__sfr __at (0xA0) P2_DATA;
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__sfr __at (0xA1) P2_PUDEN;
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__sfr __at (0xA0) P2_PUDSEL;
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__sfr __at (0xB0) P3_ALTSEL0;
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__sfr __at (0xB1) P3_ALTSEL1;
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__sfr __at (0xB0) P3_DATA;
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__sfr __at (0xB1) P3_DIR;
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__sfr __at (0xB0) P3_OD;
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__sfr __at (0xB1) P3_PUDEN;
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__sfr __at (0xB0) P3_PUDSEL;
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__sfr __at (0xBB) PASSWD;
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__sfr __at (0x87) PCON;
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__sfr __at (0xB7) PLL_CON;
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__sfr __at (0xB4) PMCON0;
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__sfr __at (0xB5) PMCON1;
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__sfr __at (0xB2) PORT_PAGE;
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__sfr __at (0xD0) PSW;
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__sfr __at (0x99) SBUF;
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__sfr __at (0x98) SCON;
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__sfr __at (0xBF) SCU_PAGE;
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__sfr __at (0x81) SP;
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__sfr __at (0xAF) SSC_BRH;
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__sfr __at (0xAE) SSC_BRL;
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__sfr __at (0xAB) SSC_CONH_O;
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__sfr __at (0xAB) SSC_CONH_P;
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__sfr __at (0xAA) SSC_CONL_O;
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__sfr __at (0xAA) SSC_CONL_P;
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__sfr __at (0xA9) SSC_PISEL;
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__sfr __at (0xAD) SSC_RBL;
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__sfr __at (0xAC) SSC_TBL;
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__sfr __at (0x8F) SYSCON0;
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__sfr __at (0xC3) T2_RC2H;
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__sfr __at (0xC2) T2_RC2L;
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__sfr __at (0xC0) T2_T2CON;
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__sfr __at (0xC5) T2_T2H;
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__sfr __at (0xC4) T2_T2L;
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__sfr __at (0xC1) T2_T2MOD;
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__sfr __at (0x88) TCON;
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__sfr __at (0x8C) TH0;
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__sfr __at (0x8D) TH1;
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__sfr __at (0x8A) TL0;
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__sfr __at (0x8B) TL1;
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__sfr __at (0x89) TMOD;
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__sfr __at (0xBB) WDTCON; // located in the mapped SFR area
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__sfr __at (0xBF) WDTH; // located in the mapped SFR area
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__sfr __at (0xBE) WDTL; // located in the mapped SFR area
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__sfr __at (0xBC) WDTREL; // located in the mapped SFR area
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__sfr __at (0xBD) WDTWINB; // located in the mapped SFR area
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__sfr __at (0xB3) XADDRH; // beware this is in an sfr page!
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__sfr __at (0xB3) _XPAGE; // this is the name SDCC expects for this sfr
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// SFR bit definitions
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/* P0 */
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__sbit __at (0x80) P0_0 ;
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__sbit __at (0x81) P0_1 ;
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__sbit __at (0x82) P0_2 ;
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__sbit __at (0x83) P0_3 ;
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__sbit __at (0x84) P0_4 ;
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__sbit __at (0x85) P0_5 ;
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/* P1 */
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__sbit __at (0x90) P1_0 ;
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__sbit __at (0x91) P1_1 ;
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__sbit __at (0x92) P1_5 ;
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__sbit __at (0x93) P1_6 ;
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__sbit __at (0x94) P1_7 ;
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/* P2 */
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__sbit __at (0xA0) P2_0 ;
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__sbit __at (0xA1) P2_1 ;
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__sbit __at (0xA2) P2_2 ;
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__sbit __at (0xA3) P2_3 ;
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__sbit __at (0xA4) P2_4 ;
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__sbit __at (0xA5) P2_5 ;
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__sbit __at (0xA6) P2_6 ;
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__sbit __at (0xA7) P2_7 ;
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/* P3 */
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__sbit __at (0xB0) P3_0 ;
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__sbit __at (0xB1) P3_1 ;
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__sbit __at (0xB2) P3_2 ;
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__sbit __at (0xB3) P3_3 ;
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__sbit __at (0xB4) P3_4 ;
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__sbit __at (0xB5) P3_5 ;
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__sbit __at (0xB6) P3_6 ;
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__sbit __at (0xB7) P3_7 ;
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// IEN0
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__sbit __at (0xAF) EA;
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__sbit __at (0xAC) ES;
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__sbit __at (0xA9) ET0;
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__sbit __at (0xAB) ET1;
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__sbit __at (0xAD) ET2;
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__sbit __at (0xA8) EX0;
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__sbit __at (0xAA) EX1;
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// IEN1
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__sbit __at (0xE8) EADC;
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__sbit __at (0xEC) ECCIP0;
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__sbit __at (0xED) ECCIP1;
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__sbit __at (0xEE) ECCIP2;
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__sbit __at (0xEF) ECCIP3;
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__sbit __at (0xE9) ESSC;
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__sbit __at (0xEA) EX2;
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__sbit __at (0xEB) EXM;
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// IP1
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__sbit __at (0xF8) PADC;
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__sbit __at (0xFC) PCCIP0;
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__sbit __at (0xFD) PCCIP1;
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__sbit __at (0xFE) PCCIP2;
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__sbit __at (0xFF) PCCIP3;
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__sbit __at (0xF9) PSSC;
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__sbit __at (0xFA) PX2;
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__sbit __at (0xFB) PXM;
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// IP
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__sbit __at (0xBC) PS;
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__sbit __at (0xB9) PT0;
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__sbit __at (0xBB) PT1;
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__sbit __at (0xBD) PT2;
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__sbit __at (0xB8) PX0;
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__sbit __at (0xBA) PX1;
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// PSW
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__sbit __at (0xD6) AC;
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__sbit __at (0xD7) CY;
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__sbit __at (0xD5) F0;
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__sbit __at (0xD1) F1;
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__sbit __at (0xD2) OV;
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__sbit __at (0xD0) P;
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__sbit __at (0xD3) RS0;
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__sbit __at (0xD4) RS1;
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// SCON
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__sbit __at (0x9A) RB8;
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__sbit __at (0x9C) REN;
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__sbit __at (0x98) RI;
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__sbit __at (0x9F) SM0;
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__sbit __at (0x9E) SM1;
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__sbit __at (0x9D) SM2;
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__sbit __at (0x9B) TB8;
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__sbit __at (0x99) TI;
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// T2_T2CON
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__sbit __at (0xC0) CP_RL2;
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__sbit __at (0xC3) EXEN2;
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__sbit __at (0xC6) EXF2;
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__sbit __at (0xC7) TF2;
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__sbit __at (0xC2) TR2;
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// TCON
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__sbit __at (0x89) IE0;
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__sbit __at (0x8B) IE1;
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__sbit __at (0x88) IT0;
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__sbit __at (0x8A) IT1;
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__sbit __at (0x8D) TF0;
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__sbit __at (0x8F) TF1;
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__sbit __at (0x8C) TR0;
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__sbit __at (0x8E) TR1;
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// Definition of the PAGE SFR
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// PORT_PAGE
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#define _pp0 PORT_PAGE=0 // PORT_PAGE postfix
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#define _pp1 PORT_PAGE=1 // PORT_PAGE postfix
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#define _pp2 PORT_PAGE=2 // PORT_PAGE postfix
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#define _pp3 PORT_PAGE=3 // PORT_PAGE postfix
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// ADC_PAGE
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#define _ad0 ADC_PAGE=0 // ADC_PAGE postfix
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#define _ad1 ADC_PAGE=1 // ADC_PAGE postfix
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#define _ad2 ADC_PAGE=2 // ADC_PAGE postfix
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#define _ad3 ADC_PAGE=3 // ADC_PAGE postfix
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#define _ad4 ADC_PAGE=4 // ADC_PAGE postfix
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#define _ad5 ADC_PAGE=5 // ADC_PAGE postfix
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#define _ad6 ADC_PAGE=6 // ADC_PAGE postfix
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// SCU_PAGE
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#define _su0 SCU_PAGE=0 // SCU_PAGE postfix
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#define _su1 SCU_PAGE=1 // SCU_PAGE postfix
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#define _su2 SCU_PAGE=2 // SCU_PAGE postfix
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// CCU_PAGE
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#define _cc0 CCU_PAGE=0 // CCU_PAGE postfix
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#define _cc1 CCU_PAGE=1 // CCU_PAGE postfix
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#define _cc2 CCU_PAGE=2 // CCU_PAGE postfix
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#define _cc3 CCU_PAGE=3 // CCU_PAGE postfix
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// FLASH_PAGE
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#define _fl0 FLASH_PAGE=0 // FLASH_PAGE postfix
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#define _fl1 FLASH_PAGE=1 // FLASH_PAGE postfix
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#define _fl2 FLASH_PAGE=2 // FLASH_PAGE postfix
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#define SST0 0x80 // Save SFR page to ST0
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#define RST0 0xC0 // Restore SFR page from ST0
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#define SST1 0x90 // Save SFR page to ST1
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#define RST1 0xD0 // Restore SFR page from ST1
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#define SST2 0xA0 // Save SFR page to ST2
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#define RST2 0xE0 // Restore SFR page from ST2
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#define SST3 0xB0 // Save SFR page to ST3
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#define RST3 0xF0 // Restore SFR page from ST3
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#define noSST 0x00 // Switch page without saving
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#define SFR_PAGE(pg,op) pg+op
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#endif
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