173 lines
7.4 KiB
C
173 lines
7.4 KiB
C
/*-------------------------------------------------------------------------
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p89v51rd2.h - Register Declarations for the Philips P89V51RD2 Processor
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Copyright (C) 2005, Jesus Calvino-Fraga / jesusc at ece.ubc.ca
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This library is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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Free Software Foundation; either version 2, or (at your option) any
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later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this library; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
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MA 02110-1301, USA.
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As a special exception, if you link this library with other files,
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some of which are compiled with SDCC, to produce an executable,
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this library does not by itself cause the resulting executable to
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be covered by the GNU General Public License. This exception does
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not however invalidate any other reasons why the executable file
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might be covered by the GNU General Public License.
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-------------------------------------------------------------------------*/
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#ifndef REG_P89V51RD2_H
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#define REG_P89V51RD2_H
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#include <8052.h> // Load definitions for the 8052
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#ifdef REG8052_H
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#undef REG8052_H
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#endif
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// Define P89V51RD2 specific registers only
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__sfr __at (0x8E) AUXR; //Auxiliary function register (Reset value 0x00).
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#define EXTRAM 0x02 //'0'=uses internal XRAM.
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#define AO 0x01 //'1'=Disables ALE generation.
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__sfr __at (0xA2) AUXR1; //Auxiliary function register 1 (Reset value 0x00).
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#define GF2 0x08 //General purpose user-defined flag.
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#define DPS 0x01 //Data pointer select.
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__sfr __at (0xFA) CCAP0H; //Module 0 Capture HIGH.
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__sfr __at (0xFB) CCAP1H; //Module 1 Capture HIGH.
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__sfr __at (0xFC) CCAP2H; //Module 2 Capture HIGH.
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__sfr __at (0xFD) CCAP3H; //Module 3 Capture HIGH.
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__sfr __at (0xFE) CCAP4H; //Module 4 Capture HIGH.
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__sfr __at (0xEA) CCAP0L; //Module 0 Capture LOW.
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__sfr __at (0xEB) CCAP1L; //Module 1 Capture LOW.
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__sfr __at (0xEC) CCAP2L; //Module 2 Capture LOW.
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__sfr __at (0xED) CCAP3L; //Module 3 Capture LOW.
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__sfr __at (0xEE) CCAP4L; //Module 4 Capture LOW.
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__sfr __at (0xDA) CCAPM0; //Module 0 Mode.
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__sfr __at (0xDB) CCAPM1; //Module 1 Mode.
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__sfr __at (0xDC) CCAPM2; //Module 2 Mode.
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__sfr __at (0xDD) CCAPM3; //Module 3 Mode.
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__sfr __at (0xDE) CCAPM4; //Module 4 Mode.
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//The preceding five registers have the following bits:
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#define ECOM 0x40 //Enable Comparator.
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#define CAPP 0x20 //1=enables positive edge capture.
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#define CAPN 0x10 //1=enables negative edge capture.
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#define MAT 0x08 //When counter matches sets CCF_n bit causing and interrupt.
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#define TOG 0x04 //Toggle output on match.
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#define PWM 0x02 //Pulse width modulation mode.
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#define ECCF 0x01 //Enable CCF interrupt.
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__sfr __at (0xD8) CCON; //PCA Counter Control (Reset value 0x00)
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__sbit __at (0xDF) CF; //PCA Counter overflow flag.
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__sbit __at (0xDE) CR ; //PCA Counter Run Control Bit. 1=counter on. 0=counter off.
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__sbit __at (0xDC) CCF4;//PCA Module 4 Interrupt Flag.
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__sbit __at (0xDB) CCF3;//PCA Module 3 Interrupt Flag.
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__sbit __at (0xDA) CCF2;//PCA Module 2 Interrupt Flag.
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__sbit __at (0xD9) CCF1;//PCA Module 1 Interrupt Flag.
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__sbit __at (0xD8) CCF0;//PCA Module 0 Interrupt Flag.
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__sfr __at (0xF9) CH; //PCA Counter HIGH.
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__sfr __at (0xE9) CL; //PCA Counter LOW.
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__sfr __at (0xD9) CMOD; //PCA Counter Mode.
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#define CIDL 0x80 //CIDL=0 program the PCA counter to work during idle mode.
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#define WDTE 0x40 //Watchdog Timer Enable.
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#define CPS1 0x04 //PCA Count Pulse Select bit 1.
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#define CPS0 0x02 //PCA Count Pulse Select bit 0.
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//00=Internal clock, Fosc/6
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//01=Internal clock, Fosc/6
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//10=Timer 0 overflow
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//11=External clock at ECI/P1.2 pin (max rate=Fosc/4)
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#define ECF 0x01 //PCA Enable Counter Overflow Interrupt.
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__sfr __at (0xB6) FST; //Flash Status Register.
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#define SB 0x40
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#define EDC 0x08
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__sfr __at (0xB1) FCF; //Flash program memory bank selection.
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#define SWR 0x02
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#define BSEL 0x01
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//Attention IEN0 is the same as register IE found in <8051.h> only bit EC added here.
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__sfr __at (0xA8) IEN0; //Interrupt Enable 1.
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__sbit __at (0xAE) EC; //PCA Interrupt Enable bit.
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__sfr __at (0xE8) IEN1; //Interrupt Enable 1
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__sbit __at (0xEB) EBO; //Brown-out Interrupt Enable. (Vector is 0x00b4).
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//Attention IP0 is the same as register IP found in <8051.h> only bit PPC added here.
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__sfr __at (0xB8) IP0; //Interrupt Priority 0 HIGH.
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__sbit __at (0xBE) PPC; //PCA Interrupt Priority low bit.
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__sfr __at (0xB7) IP0H; //Interrupt Priority 0 HIGH
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#define PPCH 0x40 //PCA Interrupt Priority High Bit.
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#define PT2H 0x20 //Timer 2 Interrupt Interrupt Priority High Bit.
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#define PSH 0x10 //Serial Port Interrupt Priority High Bit.
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#define PT1H 0x08 //Timer 1 Interrupt Priority High Bit.
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#define PX1H 0x04 //External Interrupt 1 Priority High Bit.
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#define PT0H 0x02 //Timer 0 Interrupt Priority High Bit.
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#define PX0H 0x01 //External Interrupt 0 Priority High Bit.
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__sfr __at (0xF8) IP1; //Interrupt Priority 1.
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__sbit __at (0xFB) PBO; //Brown-out Interrupt Priority Bit.
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__sfr __at (0xF7) IP1H; //Interrupt Priority 1 HIGH.
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#define PBOH 0x08 //Brown-out Interrupt Priority High Bit.
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__sfr __at (0xA9) SADDR; //Serial Port Address Register.
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__sfr __at (0xB9) SADEN; //Serial Port Address Enable.
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__sfr __at (0xD5) SPCR; //SPI Control Register (Reset value 00000000B).
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__sfr __at (0xD5) SPCTL; //SPI Control Register (This name appears also in the datasheet).
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#define SPIE 0x80 //If both SPIE and ES are set to one, SPI interrupts are enabled.
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#define SPEN 0x40 //SPI enable bit. When set enables SPI.
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#define SPE 0x40 //Same as above. This name appears also in the manual :-(
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#define DORD 0x20 //Data trans. order. 0=MSB first; 1=LSB first.
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#define MSTR 0x10 //1=master mode. 0=slave mode.
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#define CPOL 0x08 //1=SCK is high when idle (active low), 0=SCK is low when idle (active high).
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#define CPHA 0x04 //1=shift triggered on the trailing edge of SCK. 0=shift trig. on leading edge.
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#define SPR1 0x02 //SPI Clork Rate select bit 1.
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#define SPR0 0x01 //SPI Clork Rate select bit 0.
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//00 = Fosc/4
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//01 = Fosc/16
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//10 = Fosc/64
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//11 = Fosc/128
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__sfr __at (0xAA) SPSR; //SPI Configuration Register (Reset value 00000000B).
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__sfr __at (0xAA) SPCFG; //SPI Configuration Register (This name appears also in the datasheet).
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#define SPIF 0x80 //SPI interrupt flag.
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#define SPWCOL 0x40 //Write collision Flag.
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__sfr __at (0x86) SPDR; //SPI Data
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__sfr __at (0x86) SPDAT; //SPI Data (This name appears also in the datasheet).
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__sfr __at (0xC0) WDTC; //Watchdog Timer Control (Reset value 0x00).
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__sbit __at (0xC4) WDOUT;//Watchdog output enable.
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__sbit __at (0xC3) WDRE; //Watchdog timer reset enable.
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__sbit __at (0xC2) WDTS; //Watchdog timer reset flag.
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__sbit __at (0xC1) WDT; //Watchdog timer refresh.
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__sbit __at (0xC0) SWDT; //Start watchdog timer.
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__sfr __at (0x85) WDTD; //Watchdog Timer Data/Reload.
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__sfr __at (0xC9) T2MOD; //Timer 2 mode control
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#define DCEN 0x01 //Down count enable bit
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#define T2OE 0x02 //Timer 2 Output Enable bit.
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#define ENT2 0x20 //No description???
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#endif /*REG_P89V51RD2_H*/
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