262 lines
10 KiB
C
262 lines
10 KiB
C
/*-------------------------------------------------------------------------
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w7100.h - Register Declarations for WIZnet's W7100
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(Based on Internet Embedded MCU W7100 Datasheet Version 0.9 Beta)
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Copyright (C) 2009, Jesus Calvino-Fraga / jesusc at ece.ubc.ca
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This library is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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Free Software Foundation; either version 2, or (at your option) any
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later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this library; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
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MA 02110-1301, USA.
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As a special exception, if you link this library with other files,
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some of which are compiled with SDCC, to produce an executable,
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this library does not by itself cause the resulting executable to
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be covered by the GNU General Public License. This exception does
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not however invalidate any other reasons why the executable file
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might be covered by the GNU General Public License.
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-------------------------------------------------------------------------*/
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#ifndef REG_W7100_H
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#define REG_W7100_H
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#include <compiler.h>
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SFR(ACC, 0xE0); // Accumulator
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SBIT(ACC_0, 0xE0, 0);
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SBIT(ACC_1, 0xE0, 1);
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SBIT(ACC_2, 0xE0, 2);
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SBIT(ACC_3, 0xE0, 3);
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SBIT(ACC_4, 0xE0, 4);
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SBIT(ACC_5, 0xE0, 5);
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SBIT(ACC_6, 0xE0, 6);
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SBIT(ACC_7, 0xE0, 7);
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SFR(B, 0xF0); // Register B
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SBIT(B_0, 0xF0, 0);
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SBIT(B_1, 0xF0, 1);
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SBIT(B_2, 0xF0, 2);
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SBIT(B_3, 0xF0, 3);
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SBIT(B_4, 0xF0, 4);
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SBIT(B_5, 0xF0, 5);
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SBIT(B_6, 0xF0, 6);
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SBIT(B_7, 0xF0, 7);
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SFR(PCON, 0x87); // Power Configuration Register
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#define SMOD0 0x80 // Baud rate select bit
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#define SMOD1 0x40 // Not documented
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#define PWE 0x10 // Program Code Memory Write Enable Bit
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SFR(WTST, 0x92); // Program Code Memory Wait States Register
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#define WTST_2 0x04 // Wait States Register bit 2
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#define WTST_1 0x02 // Wait States Register bit 1
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#define WTST_0 0x01 // Wait States Register bit 0
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SFR(DPX0, 0x93); // Data Pointer Extended Register low
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SFR(DPX1, 0x95); // Data Pointer Extended Register high
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SFR(MXAX, 0xEA); // Data Pointer Extended Register
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SFR16E(DPTR0, 0x8382); // Data Pointer Register 0
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SFR(DPH, 0x83); // Data Pointer Register 0 high
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SFR(DPL, 0x82); // Data Pointer Register 0 low
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SFR(DPH0, 0x83); // Data Pointer Register 0 high
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SFR(DPL0, 0x82); // Data Pointer Register 0 low
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SFR16E(DPTR1, 0x8584); // Data Pointer Register 1
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SFR(DPH1, 0x85); // Data Pointer Register 1 high
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SFR(DPL1, 0x84); // Data Pointer Register 1 low
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SFR(DPS, 0x86); //Data Pointer Select Register
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#define ID1 0x80 // DPTR0, DPTR1 Operations bit 1
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#define ID0 0x40 // DPTR0, DPTR1 Operations bit 0
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#define TSL 0x20 // Toggle select enable
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#define SEL 0x01 // DPTR register select
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SFR(CKCON, 0x8E); // Clock Control Register
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#define WD1 0x80 // Watchdog Interval bit 1
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#define WD0 0x40 // Watchdog Interval bit 0
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#define MD2 0x04 // Stretch bit 2
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#define MD1 0x02 // Stretch bit 1
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#define MD0 0x01 // Stretch bit 0
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SFR(SP, 0x81); // Stack Pointer
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SFR(ISPID, 0xF1); // ID Register for ISP.
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SFR(ISPADDR16, 0xF2); // 16bit Address Register for ISP
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SFR(ISPDATA, 0xF4); // Data Register for ISP.
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SFR(CKCBK, 0xF5); // CKCON Backup Register.
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SFR(DPX0BK, 0xF6); // DPX0 Backup Register.
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SFR(DPX1BK, 0xF7); // DPX1 Backup Register.
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SFR(DPSBK, 0xF9); // DPX Backup Register.
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// WARNING: the following six definitions are not well documented
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SFR16(RAMBA16, 0xFAFB); // RAM Base Address Register.
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SFR(RAMBA16H, 0xFA);
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SFR(RAMBA16L, 0xFB);
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SFR16(RAMEA16, 0xFCFD); // RAM End Address Register.
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SFR(RAMEA16H, 0xFC);
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SFR(RAMEA16L, 0xFD);
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SFR(WCONF, 0xFF); // W7100 Configuration Register.
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#define RB 0x80 // 0 : No Reboot / 1 : Reboot after the ISP done.
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#define ISPEN 0x40 // 0 : Enable ISP in Boot built in W7100 / 1 : Disable.
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#define F64EN 0x04 // Always '0'. Read only.
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#define FB 0x02 // FLASH Busy Flag for ISP. Read only.
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#define BE 0x01 // Boot Enable (1 : Boot Running / 0 : Apps Running). Read only.
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SFR(TCON, 0x88); // Timer0, 1 configuration register.
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SBIT(IT0, 0x88, 0); // INT0 level (at 0)/edge (at 1) sensitivity.
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SBIT(IE0, 0x88, 1); // INT0 interrupt flag.
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SBIT(IT1, 0x88, 2); // INT1 level (at 0)/edge (at 1) sensitivity.
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SBIT(IE1, 0x88, 3); // INT1 interrupt flag.
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SBIT(TR0, 0x88, 4); // Timer 0 run control bit 1: Enabled, 0: Disabled.
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SBIT(TF0, 0x88, 5); // Timer 0 interrupt (overflow) flag.
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SBIT(TR1, 0x88, 6); // Timer 1 run control bit 1: Enabled, 0: Disabled.
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SBIT(TF1, 0x88, 7); // Timer 1 interrupt (overflow) flag.
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SFR(TMOD, 0x89); // Timer 0 and timer 1 control mode register.
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#define T0_M0 0x01
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#define T0_M1 0x02
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#define T0_CT 0x04
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#define T0_GATE 0x08
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#define T1_M0 0x10
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#define T1_M1 0x20
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#define T1_CT 0x40
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#define T1_GATE 0x80
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SFR(TH0, 0x8C); // Counter register of timer 0 high.
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SFR(TL0, 0x8A); // Counter register of timer 0 low.
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SFR(TH1, 0x8D); // Counter register of timer 1 high.
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SFR(TL1, 0x8B); // Counter register of timer 1 low.
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SFR(SCON, 0x98); // UART Configuration Register.
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SBIT(SM0, 0x98, 7); // UART mode bit 0.
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SBIT(SM1, 0x98, 6); // UART mode bit 1.
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SBIT(SM2, 0x98, 5); // Enable a multiprocessor communication feature.
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SBIT(REN, 0x98, 4); // Enable/Disable serial receive.
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SBIT(TB8, 0x98, 3); // The 9th transmitted data bit in Modes 2 and 3.
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SBIT(RB8, 0x98, 2); // The 9th received data bit in Modes 2 and 3.
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SBIT(TI, 0x98, 1); // UART transmitter interrupt flag.
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SBIT(RI, 0x98, 0); // UART receiver interrupt flag.
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SFR(SBUF, 0x99); // UART Buffer Register.
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SFR(IE, 0xA8); // Interrupt Enable Register.
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SBIT(EX0, 0xA8, 0); // Enable INT0 interrupt.
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SBIT(ET0, 0xA8, 1); // Enable Timer0 interrupt.
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SBIT(EX1, 0xA8, 2); // Enable INT1 interrupt.
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SBIT(ET1, 0xA8, 3); // Enable Timer1 interrupt.
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SBIT(ES, 0xA8, 4); // Enable UART interrupt.
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SBIT(ET2, 0xA8, 5); // Enable Timer2 interrupt.
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SBIT(EA, 0xA8, 7); // Enable global interrupt.
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SFR(IP, 0xB8); // Interrupt Priority Register.
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SBIT(PX0, 0xA8, 0); // INT0 priority level control.
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SBIT(PT0, 0xA8, 1); // Timer0 priority level control.
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SBIT(PX1, 0xA8, 2); // INT1 priority level control.
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SBIT(PT1, 0xA8, 3); // Timer1 priority level control.
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SBIT(PS, 0xA8, 4); // UART priority level control.
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SBIT(PT2, 0xA8, 5); // Timer2 priority level control.
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SFR(TA, 0xC7); // Timed Access Register.
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SFR(T2CON, 0xC8); // Timer 2 Configuration Register.
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SBIT(CPRL2, 0xC8, 0); // Capture/Reload select.
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SBIT(CT2, 0xC8, 1); // Timer/Counter select.
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SBIT(TR2, 0xC8, 2); // Start/Stop Timer2.
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SBIT(EXEN2, 0xC8, 3); // Enable T2EX pin functionality.
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SBIT(TCLK, 0xC8, 4); // Transmit clock enable.
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SBIT(RCLK, 0xC8, 5); // Receive clock enable.
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SBIT(EXF2, 0xC8, 6); // Indicates a Falling edge in the T2EX pin when EXEN2=1.
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SBIT(TF2, 0xC8, 7); // Timer2 overflow flag.
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SFR(RLDH, 0xCB); // Capture Registers of Timer 2 high.
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SFR(RLDL, 0xCA); // Capture Registers of Timer 2 low.
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SFR(TH2, 0xCD); // Counter Register of Timer 2 high.
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SFR(TL2, 0xCC); // Counter Register of Timer 2 low.
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SFR(PSW, 0xD0); // Program Status Word Register.
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SBIT(P, 0xD0, 0); // Parity flag.
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SBIT(F1, 0xD0, 1); // General purpose flag 1.
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SBIT(OV, 0xD0, 2); // Overflow flag.
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SBIT(RS0, 0xD0, 3); // Register bank select bit 0.
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SBIT(RS1, 0xD0, 4); // Register bank select bit 1.
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SBIT(F0, 0xD0, 5); // General purpose flag 0.
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SBIT(AC, 0xD0, 6); // Auxiliary carry.
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SBIT(CY, 0xD0, 7); // Carry flag.
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SFR(EIE, 0xE8); //Extended Interrupt Enable Register.
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SBIT(EINT2, 0xE8, 0); // Enable INT2 Interrupt.
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SBIT(EINT3, 0xE8, 1); // Enable INT3 Interrupt.
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SBIT(EINT4, 0xE8, 2); // Must be set to '0'.
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SBIT(EINT5, 0xE8, 3); // Enable TCPIPCore Interrupt.
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SBIT(EWDI, 0xE8, 4); // Enable WATCHDOG Interrupt.
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SFR(EIP, 0xF8); // Extended Interrupt Priority Register.
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SBIT(PINT2, 0xF8, 0); // INT2 priority level control.
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SBIT(PINT3, 0xF8, 1); // INT3 priority level control.
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SBIT(PINT4, 0xF8, 2); // Must be set to '0'.
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SBIT(PINT5, 0xF8, 3); // TCPIPCore Interrupt priority level control.
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SBIT(PWDI, 0xF8, 4); // WATCHDOG priority level control.
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SFR(EIF, 0x91); // Extended Interrupt Flag Register.
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#define INT2F 0x01 // INT2 interrupt flag. Must be cleared by software.
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#define INT3F 0x02 // INT3 interrupt flag. Must be cleared by software.
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#define INT4F 0x04 // Must be set to '0'.
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#define INT5F 0x08 // TCPIPCore Interrupt flag. Must be cleared by software.
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SFR(WDCON, 0xD8); // Watchdog Control Register
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SBIT(RWT, 0xD8, 0); // Reset the Watchdog Timer.
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SBIT(EWT, 0xD8, 1); // Enable the Watchdog Timer reset.
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SBIT(WTRF, 0xD8, 2); // Watchdog Timer reset Flag.
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SBIT(WDIF, 0xD8, 3); // Watchdog Interrupt Flag.
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SFR(P0, 0x80); // Port 0 Register.
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SBIT(P0_0, 0x80, 0);
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SBIT(P0_1, 0x80, 1);
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SBIT(P0_2, 0x80, 2);
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SBIT(P0_3, 0x80, 3);
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SBIT(P0_4, 0x80, 4);
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SBIT(P0_5, 0x80, 5);
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SBIT(P0_6, 0x80, 6);
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SBIT(P0_7, 0x80, 7);
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SFR(P1, 0x90); // Port 1 Register.
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SBIT(P1_0, 0x90, 0);
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SBIT(P1_1, 0x90, 1);
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SBIT(P1_2, 0x90, 2);
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SBIT(P1_3, 0x90, 3);
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SBIT(P1_4, 0x90, 4);
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SBIT(P1_5, 0x90, 5);
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SBIT(P1_6, 0x90, 6);
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SBIT(P1_7, 0x90, 7);
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SFR(P2, 0xA0); // Port 2 Register.
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SBIT(P2_0, 0xA0, 0);
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SBIT(P2_1, 0xA0, 1);
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SBIT(P2_2, 0xA0, 2);
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SBIT(P2_3, 0xA0, 3);
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SBIT(P2_4, 0xA0, 4);
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SBIT(P2_5, 0xA0, 5);
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SBIT(P2_6, 0xA0, 6);
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SBIT(P2_7, 0xA0, 7);
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SFR(P3, 0xB0); // Port 3 Register.
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SBIT(P3_0, 0xB0, 0);
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SBIT(P3_1, 0xB0, 1);
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SBIT(P3_2, 0xB0, 2);
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SBIT(P3_3, 0xB0, 3);
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SBIT(P3_4, 0xB0, 4);
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SBIT(P3_5, 0xB0, 5);
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SBIT(P3_6, 0xB0, 6);
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SBIT(P3_7, 0xB0, 7);
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#endif /*REG_W7100_H*/
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