259 lines
13 KiB
C
259 lines
13 KiB
C
/*-------------------------------------------------------------------------
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Register Declarations for the Atmel AT89C513xA Processor Range
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Copyright (C) 2010 - Anirban Brahmachari, a.brahmachari@gmail.com
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This library is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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Free Software Foundation; either version 2, or (at your option) any
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later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this library; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
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MA 02110-1301, USA.
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As a special exception, if you link this library with other files,
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some of which are compiled with SDCC, to produce an executable,
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this library does not by itself cause the resulting executable to
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be covered by the GNU General Public License. This exception does
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not however invalidate any other reasons why the executable file
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might be covered by the GNU General Public License.
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-------------------------------------------------------------------------*/
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#ifndef AT89C5131AUM_H
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#define AT89C5131AUM_H
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#include <compiler.h>
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SFR(P0, 0x80); // Port 0
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SBIT(P0_0, 0x80, 0); // Port 0 bit 0
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SBIT(P0_1, 0x80, 1); // Port 0 bit 1
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SBIT(P0_2, 0x80, 2); // Port 0 bit 2
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SBIT(P0_3, 0x80, 3); // Port 0 bit 3
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SBIT(P0_4, 0x80, 4); // Port 0 bit 4
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SBIT(P0_5, 0x80, 5); // Port 0 bit 5
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SBIT(P0_6, 0x80, 6); // Port 0 bit 6
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SBIT(P0_7, 0x80, 7); // Port 0 bit 7
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SFR(SP, 0x81); // Stack Pointer ; LSB of SPX
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SFR(DPL, 0x82); // Data Pointer Low Byte
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SFR(DPH, 0x83); // Data Pointer High Byte
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SFR(PCON, 0x87); // Power Mode Control
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SFR(TCON, 0x88); // Timer Control
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SBIT(IT0, 0x88, 0); // Ext. Interrupt 0 Type Select
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SBIT(IE0, 0x88, 1); // Ext. Interrupt 0 Flag
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SBIT(IT1, 0x88, 2); // Ext. Interrupt 1 Type Select
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SBIT(IE1, 0x88, 3); // Ext. Interrupt 1 Flag
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SBIT(TR0, 0x88, 4); // Timer 0 Run Control
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SBIT(TF0, 0x88, 5); // Timer 0 Overflow Flag
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SBIT(TR1, 0x88, 6); // Timer 1 Run Control
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SBIT(TF1, 0x88, 7); // Timer 1 Overflow Flag
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SFR(TMOD, 0x89); // Timer Mode
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SFR16E(TMR0, 0x8C8A); // Timer/Counter 0 Word
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SFR(TL0, 0x8A); // Timer/Counter 0 Low Byte
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SFR(TH0, 0x8C); // Timer/Counter 0 High Byte
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SFR16E(TMR1, 0x8D8B); // Timer/Counter 1 Word
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SFR(TL1, 0x8B); // Timer/Counter 1 Low Byte
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SFR(TH1, 0x8D); // Timer/Counter 1 High Byte
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SFR(AUXR, 0x8E); // Auxiliary Register
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SFR(CKCON0, 0x8F); // Clock Control 0
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SFR(P1, 0x90); // Port 1
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SBIT(P1_0, 0x90, 0); // Port 1 bit 0
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SBIT(P1_1, 0x90, 1); // Port 1 bit 1
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SBIT(P1_2, 0x90, 2); // Port 1 bit 2
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SBIT(P1_3, 0x90, 3); // Port 1 bit 3
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SBIT(P1_4, 0x90, 4); // Port 1 bit 4
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SBIT(P1_5, 0x90, 5); // Port 1 bit 5
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SBIT(P1_6, 0x90, 6); // Port 1 bit 6
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SBIT(P1_7, 0x90, 7); // Port 1 bit 7
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SFR(SSCON, 0x93); // Synchronous Serial Control
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SFR(SSCS, 0x94); // Synchronous Serial Control-Status
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SFR(SSDAT, 0x95); // Synchronous Serial Data
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SFR(SSADR, 0x96); // Synchronous Serial Address
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SFR(SCON, 0x98); // Serial Port 0 Control
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SBIT(RI, 0x98, 0); // Receive Interrupt Flag
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SBIT(TI, 0x98, 1); // Transmit Interrupt Flag
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SBIT(RB8, 0x98, 2); // Ninth Receive Bit
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SBIT(TB8, 0x98, 3); // Ninth Transmission Bit
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SBIT(REN, 0x98, 4); // Receive Enable
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SBIT(SM2, 0x98, 5); // Multiprocessor Communication Enable
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SBIT(SM1, 0x98, 6); // Serial Port Mode 1
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SBIT(SM0, 0x98, 7); // Serial Port Mode 0
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SBIT(FE, 0x98, 7); // Framing Error
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SFR(SBUF, 0x99); // Serial Port Data Buffer
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SFR(BRL, 0x9A); // Baud Rate Reload
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SFR(BDRCON, 0x9B); // Baud Rate Control
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SFR(KBLS, 0x9C); // Keyboard Level Selector Register
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SFR(KBE, 0x9D); // Keyboard Input Enable Register
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SFR(KBF, 0x9E); // Keyboard Flag Register
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SFR(P2, 0xA0); // Port 2
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SBIT(P2_0, 0xA0, 0); // Port 2 bit 0
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SBIT(P2_1, 0xA0, 1); // Port 2 bit 1
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SBIT(P2_2, 0xA0, 2); // Port 2 bit 2
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SBIT(P2_3, 0xA0, 3); // Port 2 bit 3
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SBIT(P2_4, 0xA0, 4); // Port 2 bit 4
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SBIT(P2_5, 0xA0, 5); // Port 2 bit 5
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SBIT(P2_6, 0xA0, 6); // Port 2 bit 6
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SBIT(P2_7, 0xA0, 7); // Port 2 bit 7
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SFR(AUXR1, 0xA2); // Auxiliary Register 1
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SFR(PLLCON, 0xA3); // PLL Control
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SFR(PLLDIV, 0xA4); // PLL Divider
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SFR(WDTRST, 0xA6); // Watchdog Timer Reset
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SFR(WDTPRG, 0xA7); // Watchdog Timer Program
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SFR(IE, 0xA8); // Interrupt Enable (traditional 8051 name)
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SFR(IEN0, 0xA8); // Interrupt Enable Control 0
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SBIT(EX0, 0xA8, 0); // Enable External Interrupt 0
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SBIT(ET0, 0xA8, 1); // Enable Timer 0 Interrupt
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SBIT(EX1, 0xA8, 2); // Enable External Interrupt 1
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SBIT(ET1, 0xA8, 3); // Enable Timer 1 Interrupt
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SBIT(ES, 0xA8, 4); // Enable Serial Port Interrupt
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SBIT(ET2, 0xA8, 5); // Enable Timer 2 Interrupt
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SBIT(EC, 0xA8, 6); // Enable PCA Interrupt
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SBIT(EA, 0xA8, 7); // Global Interrupt Enable
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SFR(SADDR, 0xA9); // Slave Address
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SFR(CKCON1, 0xAF); // Clock Control 1
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SFR(P3, 0xB0); // Port 3
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SBIT(P3_0, 0xB0, 0); // Port 3 bit 0
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SBIT(P3_1, 0xB0, 1); // Port 3 bit 1
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SBIT(P3_2, 0xB0, 2); // Port 3 bit 2
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SBIT(P3_3, 0xB0, 3); // Port 3 bit 3
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SBIT(P3_4, 0xB0, 4); // Port 3 bit 4
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SBIT(P3_5, 0xB0, 5); // Port 3 bit 5
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SBIT(P3_6, 0xB0, 6); // Port 3 bit 6
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SBIT(P3_7, 0xB0, 7); // Port 3 bit 7
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SFR(IEN1, 0xB1); // Interrupt Enable Control 1
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SFR(IPL1, 0xB2); // Interrupt Priority Control Low 1
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SFR(IPH1, 0xB3); // Interrupt Priority Control High 1
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SFR(IPH0, 0xB7); // Interrupt Priority Control High 0
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SFR(IPL0, 0xB8); // Interrupt Priority Control Low 0
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SBIT(PX0L, 0xB8, 0); // External interrupt 0 Priority bit
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SBIT(PT0L, 0xB8, 1); // Timer 0 overflow interrupt Priority bit
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SBIT(PX1L, 0xB8, 2); // External interrupt 1 Priority bit
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SBIT(PT1L, 0xB8, 3); // Timer 1 overflow interrupt Priority bit
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SBIT(PSL, 0xB8, 4); // Serial port Priority bit
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SBIT(PT2L, 0xB8, 5); // Timer 2 overflow interrupt Priority bit
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SBIT(PPCL, 0xB8, 6); // PCA interrupt Priority bit
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SFR(SADEN, 0xB9); // Slave Address Mask
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SFR16E(UFNUM, 0xBBBA); // USB Frame Number Word
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SFR(UFNUML, 0xBA); // USB Frame Number Low
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SFR(UFNUMH, 0xBB); // USB Frame Number High
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SFR(USBCON, 0xBC); // USB Global Control
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SFR(USBINT, 0xBD); // USB Global Interrupt
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SFR(USBIEN, 0xBE); // USB Global Interrupt Enable
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SFR(P4, 0xC0); // Port 4
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SBIT(P4_0, 0xC0, 0); // Port 4 bit 0
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SBIT(P4_1, 0xC0, 1); // Port 4 bit 1
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SFR(UEPIEN, 0xC2); // USB Endpoint Interrupt Enable
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SFR(SPCON, 0xC3); // Serial Peripheral Control
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SFR(SPSTA, 0xC4); // Serial Peripheral Status-Control
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SFR(SPDAT, 0xC5); // Serial Peripheral Data
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SFR(USBADDR, 0xC6); // USB Address
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SFR(UEPNUM, 0xC7); // USB Endpoint Number
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SFR(T2CON, 0xC8); // Timer 2 Control
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SBIT(CP_RL2, 0xC8, 0); // Timer 2 Capture/Reload bit
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SBIT(C_T2, 0xC8, 1); // Timer/Counter 2 select bit
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SBIT(TR2, 0xC8, 2); // Timer 2 Run control bit
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SBIT(EXEN2, 0xC8, 3); // Timer 2 External Enable bit
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SBIT(TCLK, 0xC8, 4); // Transmit Clock bit
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SBIT(RCLK, 0xC8, 5); // Receive Clock bit
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SBIT(EXF2, 0xC8, 6); // Timer 2 External Flag
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SBIT(TF2, 0xC8, 7); // Timer 2 overflow Flag
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SFR(T2MOD, 0xC9); // Timer 2 Mode
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SFR16E(RCAP2, 0xCBCA); // Timer/Counter 2 Reload/Capture Word
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SFR(RCAP2L, 0xCA); // Timer/Counter 2 Reload/Capture Low byte
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SFR(RCAP2H, 0xCB); // Timer/Counter 2 Reload/Capture High byte
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SFR16E(TMR2, 0xCDCC); // Timer/Counter 2 Word
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SFR(TL2, 0xCC); // Timer/Counter 2 Low Byte
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SFR(TH2, 0xCD); // Timer/Counter 2 High Byte
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SFR(UEPSTAX, 0xCE); // USB Endpoint X Status
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SFR(UEPDATX, 0xCF); // USB Endpoint X FIFO Data
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SFR(PSW, 0xD0); // Program Status Word
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SBIT(P, 0xD0, 0); // Parity Flag
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SBIT(F1, 0xD0, 1); // User-Defined Flag
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SBIT(OV, 0xD0, 2); // Overflow Flag
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SBIT(RS0, 0xD0, 3); // Register Bank Select 0
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SBIT(RS1, 0xD0, 4); // Register Bank Select 1
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SBIT(F0, 0xD0, 5); // User-Defined Flag
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SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag
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SBIT(CY, 0xD0, 7); // Carry Flag
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SFR(FCON, 0xD1); // Flash Control
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SFR(EECON, 0xD2); // EEPROM Contol
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SFR(UEPCONX, 0xD4); // USB Endpoint X Control
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SFR(UEPRST, 0xD5); // USB Endpoint Reset
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SFR(CCON, 0xD8); // PCA Timer/Counter Control
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SBIT(CCF0, 0xD8,0); // PCA Module 0 interrupt flag
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SBIT(CCF1, 0xD8,1); // PCA Module 1 interrupt flag
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SBIT(CCF2, 0xD8,2); // PCA Module 2 interrupt flag
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SBIT(CCF3, 0xD8,3); // PCA Module 3 interrupt flag
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SBIT(CCF4, 0xD8,4); // PCA Module 4 interrupt flag
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SBIT(CR, 0xD8,6); // PCA Counter Run control bit
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SBIT(CF, 0xD8,7); // PCA Counter Overflow flag
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SFR(CMOD, 0xD9); // PCA Timer/Counter Mode
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SFR(CCAPM0, 0xDA); // PCA Timer/Counter 0 Mode
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SFR(CCAPM1, 0xDB); // PCA Timer/Counter 1 Mode
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SFR(CCAPM2, 0xDC); // PCA Timer/Counter 2 Mode
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SFR(CCAPM3, 0xDD); // PCA Timer/Counter 3 Mode
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SFR(CCAPM4, 0xDE); // PCA Timer/Counter 4 Mode
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SFR(ACC, 0xE0); // Accumulator
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SFR16E(UBYCTX, 0xE3E2); // USB Byte Counter Word
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SFR(UBYCTLX, 0xE2); // USB Byte Counter Low
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SFR(UBYCTHX, 0xE3); // USB Byte Counter High
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SFR16E(PCA, 0xF9E9); // PCA Timer/Counter Word
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SFR(CL, 0xE9); // PCA Timer/Counter Low byte
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SFR(CH, 0xF9); // PCA Timer/Counter High byte
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SFR16E(CCAP0, 0xFAEA); // PCA Compare Capture Module 0 Word
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SFR(CCAP0L, 0xEA); // PCA Compare Capture Module 0 Low byte
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SFR(CCAP0H, 0xFA); // PCA Compare Capture Module 0 High byte
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SFR16E(CCAP1, 0xFBEB); // PCA Compare Capture Module 1 Word
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SFR(CCAP1L, 0xEB); // PCA Compare Capture Module 1 Low byte
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SFR(CCAP1H, 0xFB); // PCA Compare Capture Module 1 High byte
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SFR16E(CCAP2, 0xFCEC); // PCA Compare Capture Module 2 Word
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SFR(CCAP2L, 0xEC); // PCA Compare Capture Module 2 Low byte
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SFR(CCAP2H, 0xFC); // PCA Compare Capture Module 2 High byte
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SFR16E(CCAP3, 0xFDED); // PCA Compare Capture Module 3 Word
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SFR(CCAP3L, 0xED); // PCA Compare Capture Module 3 Low byte
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SFR(CCAP3H, 0xFD); // PCA Compare Capture Module 3 High byte
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SFR16E(CCAP4, 0xFEEE); // PCA Compare Capture Module 4 Word
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SFR(CCAP4L, 0xEE); // PCA Compare Capture Module 4 Low byte
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SFR(CCAP4H, 0xFE); // PCA Compare Capture Module 4 High byte
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SFR(B, 0xF0); // B Register
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SFR(LEDCON, 0xF1); // LED Control
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SFR(UEPINT, 0xF8); // USB Endpoint Interrupt
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SBIT(EP0INT, 0xF8,0); // Endpoint 0 Interrupt
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SBIT(EP1INT, 0xF8,1); // Endpoint 1 Interrupt
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SBIT(EP2INT, 0xF8,2); // Endpoint 2 Interrupt
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SBIT(EP3INT, 0xF8,3); // Endpoint 3 Interrupt
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SBIT(EP4INT, 0xF8,4); // Endpoint 4 Interrupt
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SBIT(EP5INT, 0xF8,5); // Endpoint 5 Interrupt
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SBIT(EP6INT, 0xF8,6); // Endpoint 6 Interrupt
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/* Predefined SFR Bit Masks */
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#define PCON_IDLE 0x01 /* PCON */
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#define PCON_STOP 0x02 /* PCON */
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/* Interrupts */
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#define INT_RESET 0 // Reset
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#define INT_EXT0 1 // External Interrupt 0
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#define INT_TIMER0 2 // Timer0 Overflow
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#define INT_EXT1 3 // External Interrupt 1
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#define INT_TIMER1 4 // Timer1 Overflow
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#define INT_UART0 5 // Serial Port 0
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#define INT_TIMER2 6 // Timer2 Overflow
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#define INT_PCA 7 // Programmable Counter Array
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#define INT_KEYBOARD 8 // Keyboard on P1
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#define INT_TWI 9 // Two Wire Interface
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#define INT_SPI 10 // Serial Peripheral Interface
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// 11 Reserved
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// 12 Reserved
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// 13 Reserved
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#define INT_USB 14 // USB events
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// 15 Reserved
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#endif
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