181 lines
4.8 KiB
C
181 lines
4.8 KiB
C
/*-------------------------------------------------------------------------
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8051.h: Register Declarations for the Intel 8051 Processor
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Copyright (C) 2000, Bela Torok / bela.torok@kssg.ch
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This library is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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Free Software Foundation; either version 2, or (at your option) any
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later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this library; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
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MA 02110-1301, USA.
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As a special exception, if you link this library with other files,
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some of which are compiled with SDCC, to produce an executable,
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this library does not by itself cause the resulting executable to
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be covered by the GNU General Public License. This exception does
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not however invalidate any other reasons why the executable file
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might be covered by the GNU General Public License.
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-------------------------------------------------------------------------*/
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#ifndef REG8051_H
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#define REG8051_H
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#include "lint.h"
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/* BYTE Register */
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__sfr __at (0x80) P0 ;
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__sfr __at (0x81) SP ;
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__sfr __at (0x82) DPL ;
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__sfr __at (0x83) DPH ;
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__sfr __at (0x87) PCON ;
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__sfr __at (0x88) TCON ;
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__sfr __at (0x89) TMOD ;
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__sfr __at (0x8A) TL0 ;
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__sfr __at (0x8B) TL1 ;
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__sfr __at (0x8C) TH0 ;
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__sfr __at (0x8D) TH1 ;
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__sfr __at (0x90) P1 ;
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__sfr __at (0x98) SCON ;
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__sfr __at (0x99) SBUF ;
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__sfr __at (0xA0) P2 ;
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__sfr __at (0xA8) IE ;
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__sfr __at (0xB0) P3 ;
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__sfr __at (0xB8) IP ;
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__sfr __at (0xD0) PSW ;
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__sfr __at (0xE0) ACC ;
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__sfr __at (0xF0) B ;
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/* BIT Register */
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/* P0 */
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__sbit __at (0x80) P0_0 ;
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__sbit __at (0x81) P0_1 ;
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__sbit __at (0x82) P0_2 ;
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__sbit __at (0x83) P0_3 ;
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__sbit __at (0x84) P0_4 ;
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__sbit __at (0x85) P0_5 ;
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__sbit __at (0x86) P0_6 ;
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__sbit __at (0x87) P0_7 ;
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/* TCON */
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__sbit __at (0x88) IT0 ;
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__sbit __at (0x89) IE0 ;
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__sbit __at (0x8A) IT1 ;
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__sbit __at (0x8B) IE1 ;
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__sbit __at (0x8C) TR0 ;
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__sbit __at (0x8D) TF0 ;
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__sbit __at (0x8E) TR1 ;
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__sbit __at (0x8F) TF1 ;
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/* P1 */
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__sbit __at (0x90) P1_0 ;
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__sbit __at (0x91) P1_1 ;
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__sbit __at (0x92) P1_2 ;
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__sbit __at (0x93) P1_3 ;
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__sbit __at (0x94) P1_4 ;
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__sbit __at (0x95) P1_5 ;
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__sbit __at (0x96) P1_6 ;
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__sbit __at (0x97) P1_7 ;
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/* SCON */
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__sbit __at (0x98) RI ;
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__sbit __at (0x99) TI ;
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__sbit __at (0x9A) RB8 ;
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__sbit __at (0x9B) TB8 ;
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__sbit __at (0x9C) REN ;
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__sbit __at (0x9D) SM2 ;
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__sbit __at (0x9E) SM1 ;
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__sbit __at (0x9F) SM0 ;
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/* P2 */
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__sbit __at (0xA0) P2_0 ;
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__sbit __at (0xA1) P2_1 ;
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__sbit __at (0xA2) P2_2 ;
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__sbit __at (0xA3) P2_3 ;
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__sbit __at (0xA4) P2_4 ;
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__sbit __at (0xA5) P2_5 ;
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__sbit __at (0xA6) P2_6 ;
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__sbit __at (0xA7) P2_7 ;
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/* IE */
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__sbit __at (0xA8) EX0 ;
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__sbit __at (0xA9) ET0 ;
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__sbit __at (0xAA) EX1 ;
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__sbit __at (0xAB) ET1 ;
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__sbit __at (0xAC) ES ;
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__sbit __at (0xAF) EA ;
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/* P3 */
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__sbit __at (0xB0) P3_0 ;
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__sbit __at (0xB1) P3_1 ;
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__sbit __at (0xB2) P3_2 ;
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__sbit __at (0xB3) P3_3 ;
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__sbit __at (0xB4) P3_4 ;
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__sbit __at (0xB5) P3_5 ;
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__sbit __at (0xB6) P3_6 ;
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__sbit __at (0xB7) P3_7 ;
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__sbit __at (0xB0) RXD ;
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__sbit __at (0xB1) TXD ;
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__sbit __at (0xB2) INT0 ;
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__sbit __at (0xB3) INT1 ;
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__sbit __at (0xB4) T0 ;
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__sbit __at (0xB5) T1 ;
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__sbit __at (0xB6) WR ;
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__sbit __at (0xB7) RD ;
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/* IP */
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__sbit __at (0xB8) PX0 ;
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__sbit __at (0xB9) PT0 ;
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__sbit __at (0xBA) PX1 ;
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__sbit __at (0xBB) PT1 ;
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__sbit __at (0xBC) PS ;
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/* PSW */
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__sbit __at (0xD0) P ;
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__sbit __at (0xD1) F1 ;
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__sbit __at (0xD2) OV ;
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__sbit __at (0xD3) RS0 ;
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__sbit __at (0xD4) RS1 ;
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__sbit __at (0xD5) F0 ;
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__sbit __at (0xD6) AC ;
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__sbit __at (0xD7) CY ;
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/* BIT definitions for bits that are not directly accessible */
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/* PCON bits */
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#define IDL 0x01
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#define PD 0x02
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#define GF0 0x04
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#define GF1 0x08
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#define SMOD 0x80
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/* TMOD bits */
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#define T0_M0 0x01
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#define T0_M1 0x02
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#define T0_CT 0x04
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#define T0_GATE 0x08
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#define T1_M0 0x10
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#define T1_M1 0x20
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#define T1_CT 0x40
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#define T1_GATE 0x80
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#define T0_MASK 0x0F
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#define T1_MASK 0xF0
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/* Interrupt numbers: address = (number * 8) + 3 */
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#define IE0_VECTOR 0 /* 0x03 external interrupt 0 */
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#define TF0_VECTOR 1 /* 0x0b timer 0 */
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#define IE1_VECTOR 2 /* 0x13 external interrupt 1 */
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#define TF1_VECTOR 3 /* 0x1b timer 1 */
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#define SI0_VECTOR 4 /* 0x23 serial port 0 */
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#endif
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