385 lines
17 KiB
C
385 lines
17 KiB
C
/*-------------------------------------------------------------------------
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ADuC84x.h: Register Declarations for Analog Devices
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ADuC841/ADuC842/ADuC843 (Based on datasheet Rev 0, 11/2003 )
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Copyright (C) 2007, Jesus Calvino-Fraga / jesusc at ece.ubc.ca
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This library is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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Free Software Foundation; either version 2, or (at your option) any
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later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this library; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
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MA 02110-1301, USA.
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As a special exception, if you link this library with other files,
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some of which are compiled with SDCC, to produce an executable,
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this library does not by itself cause the resulting executable to
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be covered by the GNU General Public License. This exception does
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not however invalidate any other reasons why the executable file
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might be covered by the GNU General Public License.
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-------------------------------------------------------------------------*/
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#ifndef REG_ADUC84X_H
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#define REG_ADUC84X_H
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#include <compiler.h>
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SFR(CFG841, 0xAF); // ADuC841 Configuration SFR.
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SFR(CFG842, 0xAF); // ADuC842/ADuC843 Configuration SFR.
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//For the two SFRs above these are the bits. Warning: some are different for
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//the ADuC841 and ADuC842/ADuC843. Check the datasheet!
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#define EPM2 0x10 // Flash/EE Controller and PWM Clock Frequency Configuration Bit 2.
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#define EPM1 0x08 // Flash/EE Controller and PWM Clock Frequency Configuration Bit 1.
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#define EPM0 0x04 // Flash/EE Controller and PWM Clock Frequency Configuration Bit 0.
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#define EXSP 0x80 // Extended SP Enable.
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#define PWPO 0x40 // PWM Pin Out Selection.
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#define DBUF 0x20 // DAC Output Buffer.
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#define EXTCLK 0x10 // Set by the user to 1 to select an external clock input on P3.4.
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#define MSPI 0x02 // Set to 1 by the user to move the SPI functionality of.
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#define XRAMEN 0x01 // XRAM Enable Bit.
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SFR(SP, 0x81); // Stack Pointer.
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SFR(SPH, 0xB7); // Stack pointer high.
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SFR(DPL, 0x82); // Data Pointer Low.
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SFR(DPH, 0x83); // Data Pointer High.
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SFR(DPP, 0x84); // Data Pointer Page Byte.
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SFR(DPCON, 0xA7); // Data Pointer Control SFR.
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SFR(PCON, 0x87); // Power Control.
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#define SMOD 0x80 //Double UART Baud Rate.
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#define SERIPD 0x40 //I2C/SPI Power-Down Interrupt Enable.
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#define INT0PD 0x20 //INT0 Power-Down Interrupt Enable.
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#define ALEOFF 0x10 //Disable ALE Output.
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#define GF1 0x08 //General-Purpose Flag Bit.
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#define GF0 0x04 //General-Purpose Flag Bit.
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#define PD 0x02 //Power-Down Mode Enable.
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#define IDL 0x01 //Idle Mode Enable.
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SFR(TCON, 0x88); // Timer/Counter Control.
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SBIT(TF1, 0x88, 7); // Timer 1 overflow flag.
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SBIT(TR1, 0x88, 6); // Timer 1 run control flag.
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SBIT(TF0, 0x88, 5); // Timer 0 overflow flag.
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SBIT(TR0, 0x88, 4); // Timer 0 run control flag.
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SBIT(IE1, 0x88, 3); // Interrupt 1 flag.
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SBIT(IT1, 0x88, 2); // Interrupt 1 type control bit.
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SBIT(IE0, 0x88, 1); // Interrupt 0 flag.
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SBIT(IT0, 0x88, 0); // Interrupt 0 type control bit.
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SFR(TMOD, 0x89); // Timer/Counter Mode Control.
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#define GATE1 0x80 // External enable for timer 1.
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#define C_T1 0x40 // Timer or counter select for timer 1.
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#define M1_1 0x20 // Operation mode bit 1 for timer 1.
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#define M0_1 0x10 // Operation mode bit 0 for timer 1.
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#define GATE0 0x08 // External enable for timer 0.
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#define C_T0 0x04 // Timer or counter select for timer 0.
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#define M1_0 0x02 // Operation mode bit 1 for timer 0.
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#define M0_0 0x01 // Operation mode bit 0 for timer 0.
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SFR(TL0, 0x8A); // Timer 0 LSB.
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SFR(TL1, 0x8B); // Timer 1 LSB.
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SFR(TH0, 0x8C); // Timer 0 MSB.
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SFR(TH1, 0x8D); // Timer 1 MSB.
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SFR(P0, 0x80); // Port 0
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SBIT(P0_0, 0x80, 0); // Port 0 bit 0.
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SBIT(P0_1, 0x80, 1); // Port 0 bit 1.
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SBIT(P0_2, 0x80, 2); // Port 0 bit 2.
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SBIT(P0_3, 0x80, 3); // Port 0 bit 3.
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SBIT(P0_4, 0x80, 4); // Port 0 bit 4.
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SBIT(P0_5, 0x80, 5); // Port 0 bit 5.
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SBIT(P0_6, 0x80, 6); // Port 0 bit 6.
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SBIT(P0_7, 0x80, 7); // Port 0 bit 7.
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SFR(P1, 0x90); // Port 1
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SBIT(P1_0, 0x90, 0); // Port 1 bit 0.
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SBIT(P1_1, 0x90, 1); // Port 1 bit 1.
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SBIT(P1_2, 0x90, 2); // Port 1 bit 2.
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SBIT(P1_3, 0x90, 3); // Port 1 bit 3.
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SBIT(P1_4, 0x90, 4); // Port 1 bit 4.
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SBIT(P1_5, 0x90, 5); // Port 1 bit 5.
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SBIT(P1_6, 0x90, 6); // Port 1 bit 6.
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SBIT(P1_7, 0x90, 7); // Port 1 bit 7.
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// Alternate names
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SBIT(T2EX, 0x90, 1); //Capture/reload trigger for Counter 2.
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SBIT(T2, 0x90, 0); //Input to Timer/Counter 2.
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SFR(P2, 0xA0); // Port 2
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SBIT(P2_0, 0xA0, 0); // Port 2 bit 0.
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SBIT(P2_1, 0xA0, 1); // Port 2 bit 1.
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SBIT(P2_2, 0xA0, 2); // Port 2 bit 2.
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SBIT(P2_3, 0xA0, 3); // Port 2 bit 3.
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SBIT(P2_4, 0xA0, 4); // Port 2 bit 4.
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SBIT(P2_5, 0xA0, 5); // Port 2 bit 5.
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SBIT(P2_6, 0xA0, 6); // Port 2 bit 6.
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SBIT(P2_7, 0xA0, 7); // Port 2 bit 7.
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SFR(P3, 0xB0); // Port 3
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SBIT(P3_0, 0xB0, 0); // Port 3 bit 0.
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SBIT(P3_1, 0xB0, 1); // Port 3 bit 1.
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SBIT(P3_2, 0xB0, 2); // Port 3 bit 2.
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SBIT(P3_3, 0xB0, 3); // Port 3 bit 3.
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SBIT(P3_4, 0xB0, 4); // Port 3 bit 4.
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SBIT(P3_5, 0xB0, 5); // Port 3 bit 5.
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SBIT(P3_6, 0xB0, 6); // Port 3 bit 6.
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SBIT(P3_7, 0xB0, 7); // Port 3 bit 7.
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// Alternate names.
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SBIT(RXD, 0xB0, 0);
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SBIT(TXD, 0xB0, 1);
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SBIT(INT0, 0xB0, 2);
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SBIT(INT1, 0xB0, 3);
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SBIT(T0, 0xB0, 4);
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SBIT(T1, 0xB0, 5);
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SBIT(WR, 0xB0, 6);
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SBIT(RD, 0xB0, 7);
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SFR(I2CADD, 0x9B); // I2C Address Register 1.
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SFR(I2CADD1, 0x91); // I2C Address Register 2.
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SFR(I2CADD2, 0x92); // I2C Address Register 3.
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SFR(I2CADD3, 0x93); // I2C Address Register 4.
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SFR(I2CDAT, 0x9A); // I2C Data Register.
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SFR(SCON, 0x98); // Serial Port Control.
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SBIT(SM0, 0x98, 7); // Serial Port Mode Bit 0.
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SBIT(SM1, 0x98, 6); // Serial Port Mode Bit 1.
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SBIT(SM2, 0x98, 5); // Serial Port Mode Bit 2.
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SBIT(REN, 0x98, 4); // Enables serial reception.
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SBIT(TB8, 0x98, 3); // The 9th data bit that will be transmitted in Modes 2 and 3.
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SBIT(RB8, 0x98, 2); // In Modes 2 and 3, the 9th data bit that was received.
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SBIT(TI, 0x98, 1); // Transmit interrupt flag.
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SBIT(RI, 0x98, 0); // Receive interrupt flag.
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SFR(SBUF, 0x99); // Serial Data Buffer.
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//For these two, you may want to check page 68 of the datasheet...
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SFR(T3FD, 0x9D); // Fractional divider ratio.
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SFR(T3CON, 0x9E); // T3CON is the baud rate control SFR, allowing Timer 3 to be
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// used to set up the UART baud rate, and setting up the binary
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// divider (DIV).
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#define T3BAUDEN 0x80 // T3 UART BAUD Enable.
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#define DIV2 0x04 // Binary Divider Factor bit 3.
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#define DIV1 0x02 // Binary Divider Factor bit 2.
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#define DIV0 0x01 // Binary Divider Factor bit 1.
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SFR(TIMECON, 0xA1); // TIC Control Register.
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#define TFH 0x40 // Twenty-Four Hour Select Bit.
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#define ITS1 0x20 // Interval Timebase Selection Bit 1.
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#define ITS0 0x10 // Interval Timebase Selection Bit 1.
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#define STI 0x08 // Single Time Interval Bit.
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#define TII 0x04 // TIC Interrupt Bit.
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#define TIEN 0x02 // Time Interval Enable Bit.
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#define TCEN 0x01 // Time Clock Enable Bit.
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SFR(HTHSEC, 0xA2); // Hundredths Seconds Time Register.
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SFR(SEC, 0xA3); // Seconds Time Register.
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SFR(MIN, 0xA4); // Minutes Time Register.
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SFR(HOUR, 0xA5); // Hours Time Register.
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SFR(INTVAL, 0xA6); // User Time Interval Select Register.
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SFR(IE, 0xA8); // Interrupt Enable.
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SBIT(EA, 0xA8, 7); // Global Interrupt Enable.
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SBIT(EADC, 0xA8, 6); // ADC Interrupt Enable.
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SBIT(ET2, 0xA8, 5); // Timer 2 Interrupt Enable.
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SBIT(ES, 0xA8, 4); // Serial Interrupt Enable.
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SBIT(ET1, 0xA8, 3); // Timer 1 Interrupt Enable.
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SBIT(EX1, 0xA8, 2); // External 1 Interrupt Enable.
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SBIT(ET0, 0xA8, 1); // Timer 0 Interrupt Enable.
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SBIT(EX0, 0xA8, 0); // External 0 Interrupt Enable.
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SFR(IEIP2, 0xA9); // Secondary Interrupt Enable Register
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#define PTI 0x40 // Priority for time interval interrupt.
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#define PPSM 0x20 // Priority for power supply monitor interrupt.
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#define PSI2 0x10 // Priority for SPI/I2C interrupt. Same name as bit in IP???
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#define ETI 0x04 // Enable time interval counter interrupts.
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#define EPSMI 0x02 // Enable power supply monitor interrupts.
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#define ESI 0x01 // Enable SPI or I2C serial port interrupts.
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SFR(PWMCON, 0xAE); //PWM control.
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#define SNGL 0x80 // Turns off PMW output at P2.6 or P3.4.
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#define MD2 0x40 // PWM Mode Bit 2.
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#define MD1 0x20 // PWM Mode Bit 2.
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#define MD0 0x10 // PWM Mode Bit 2.
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#define CDIV1 0x08 // PWM Clock Divider bit 1.
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#define CDIV0 0x04 // PWM Clock Divider bit 1.
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#define CSEL1 0x02 // PWM Clock Select bit 1. (Typo in datasheet???)
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#define CSEL0 0x01 // PWM Clock Select bit 0.
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SFR(PWM0L, 0xB1); // PWM 0 duty cycle low.
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SFR(PWM0H, 0xB2); // PWM 0 duty cycle high.
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SFR(PWM1L, 0xB3); // PWM 1 duty cycle low.
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SFR(PWM1H, 0xB4); // PWM 1 duty cycle high.
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SFR(IP, 0xB8); // Interrupt Priority Reg.
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SBIT(PSI, 0xB8, 7); // Priority for SPI/I2C interrupt.
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SBIT(PADC, 0xB8, 6); // ADC interrupt priority bit.
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SBIT(PT2, 0xB8, 5); // Timer 2 interrupt priority bit.
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SBIT(PS, 0xB8, 4); // Serial Port interrupt priority bit.
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SBIT(PT1, 0xB8, 3); // Timer 1 interrupt priority bit.
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SBIT(PX1, 0xB8, 2); // External interrupt 1 priority bit.
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SBIT(PT0, 0xB8, 1); // Timer 0 interrupt priority bit.
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SBIT(PX0, 0xB8, 0); // External interrupt 0 priority bit.
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SFR(ECON, 0xB9); // Flash/EE Memory Control SFR.
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SFR(EDATA1, 0xBC); // EE page data byte 1.
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SFR(EDATA2, 0xBD); // EE page data byte 2.
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SFR(EDATA3, 0xBE); // EE page data byte 3.
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SFR(EDATA4, 0xBF); // EE page data byte 4.
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SFR(EADRL, 0xC6); // EE address low.
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SFR(EADRH, 0xC7); // EE address high.
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SFR(WDCON, 0xC0); //Watchdog Timer Control Register.
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SBIT(PRE3, 0xc0, 7); // Timeout period bit 4.
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SBIT(PRE2, 0xc0, 6); // Timeout period bit 3.
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SBIT(PRE1, 0xc0, 5); // Timeout period bit 2.
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SBIT(PRE0, 0xc0, 4); // Timeout period bit 1.
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SBIT(WDIR, 0xc0, 3); // Watchdog Interrupt Response Enable Bit.
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SBIT(WDS, 0xc0, 2); // Watchdog Status Bit.
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SBIT(WDE, 0xc0, 1); // Watchdog Enable Bit.
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SBIT(WDWR, 0xc0, 0); // Watchdog Write Enable Bit.
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SFR(CHIPID, 0xC2); // System Self-Identification? WARNING: No description in the datasheet.
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SFR(T2CON, 0xC8); // Timer / Counter 2 Control.
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SBIT(TF2, 0xC8, 7); // Timer 2 overflow flag.
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SBIT(EXF2, 0xC8, 6); // Timer 2 external flag.
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SBIT(RCLK, 0xC8, 5); // Receive clock flag.
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SBIT(TCLK, 0xC8, 4); // Transmit clock flag.
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SBIT(EXEN2, 0xC8, 3); // Timer 2 external enable flag.
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SBIT(TR2, 0xC8, 2); // Start/stop control for timer 2.
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SBIT(CNT2, 0xC8, 1); // Timer or coutner select.
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SBIT(CAP2, 0xC8, 0); // Capture/reload flag.
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SFR(RCAP2L, 0xCA); // Timer 2 Capture LSB.
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SFR(RCAP2H, 0xCB); // Timer 2 Capture MSB.
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SFR(TL2, 0xCC); // Timer 2 LSB.
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SFR(TH2, 0xCD); // Timer 2 MSB.
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SFR(PSW, 0xD0); // Program Status Word.
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SBIT(CY, 0xD0, 7); // Carry Flag.
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SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag.
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SBIT(F0, 0xD0, 5); // User-Defined Flag.
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SBIT(RS1, 0xD0, 4); // Register Bank Select 1.
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SBIT(RS0, 0xD0, 3); // Register Bank Select 0.
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SBIT(OV, 0xD0, 2); // Overflow Flag.
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SBIT(F1, 0xD0, 1); // User-Defined Flag.
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SBIT(P, 0xD0, 0); // Parity Flag.
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SFR(DMAL, 0xD2); // DMA mode address pointer low.
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SFR(DMAH, 0xD3); // DMA mode address pointer high.
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SFR(DMAP, 0xD4); // DMA mode address pointer page. (?)
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SFR(PLLCON, 0xD7); // PLL Control Register.
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SFR(PSMCON, 0xDF); // Power supply monitor.
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#define CMPD 0x40 // DVDD Comparator Bit.
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#define PSMI 0x20 // Power Supply Monitor Interrupt Bit.
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#define TPD1 0x10 // DVDD Trip Point Selection Bit 2.
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#define TPD0 0x08 // DVDD Trip Point Selection Bit 1.
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#define PSMEN 0x01 // Power Supply Monitor Enable Bit.
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SFR(ACC, 0xE0); // Accumulator
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SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0.
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SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1.
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SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2.
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SBIT(ACC_3, 0xE0, 3); // Accumulator bit 3.
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SBIT(ACC_4, 0xE0, 4); // Accumulator bit 4.
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SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5.
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SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6.
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SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7.
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SFR(I2CCON, 0xE8); // I2C Control Register
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// Master mode
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SBIT(MDO, 0xE8, 7); // I2C Software Master Data Output Bit.
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SBIT(MDE, 0xE8, 6); // I2C Software Master Data Output Enable Bit.
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SBIT(MCO, 0xE8, 5); // I2C Software Master Clock Output Bit.
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SBIT(MDI, 0xE8, 4); // I2C Software Master Data Input Bit.
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// Slave mode
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SBIT(I2CSI, 0xE8, 7); // I2C Stop Interrupt Enable Bit.
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SBIT(I2CGC, 0xE8, 6); // I2C General Call Status Bit.
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SBIT(I2CID1, 0xE8, 5); // I2C Interrupt Decode Bit 2.
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SBIT(I2CID0, 0xE8, 4); // I2C Interrupt Decode Bit 1.
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SBIT(I2CM, 0xE8, 3); // I2C Master/Slave Mode Bit.
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SBIT(I2CRS, 0xE8, 2); // I2C Reset Bit.
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SBIT(I2CTX, 0xE8, 1); // I2C Direction Transfer Bit.
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SBIT(I2CI, 0xE8, 0); // I2C Interrupt Bit.
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SFR(B, 0xF0); // B Register
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SBIT(B_0, 0xF0, 0); // Register B bit 0.
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SBIT(B_1, 0xF0, 1); // Register B bit 1.
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SBIT(B_2, 0xF0, 2); // Register B bit 2.
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SBIT(B_3, 0xF0, 3); // Register B bit 3.
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SBIT(B_4, 0xF0, 4); // Register B bit 4.
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SBIT(B_5, 0xF0, 5); // Register B bit 5.
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SBIT(B_6, 0xF0, 6); // Register B bit 6.
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SBIT(B_7, 0xF0, 7); // Register B bit 7.
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SFR(ADCCON1, 0xEF); //ADC Control SFR 1
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//WARNING: bit 7 is named MD1 in the datasheet, but that name is already used.
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#define MD 0x80 // The mode bit selects the active operating mode of the ADC.
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#define EXT_REF 0x40 // Set by the user to select an external reference.
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#define CK1 0x20 // The ADC clock divide bit 1.
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#define CK0 0x10 // The ADC clock divide bit 0.
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#define AQ1 0x08 // ADC acquisition select bit 1.
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#define AQ0 0x04 // ADC acquisition select bit 0.
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#define T2C 0x02 // The Timer 2 conversion bit.
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#define EXC 0x01 // The external trigger enable bit.
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SFR(ADCCON2, 0xD8); // ADC Control SFR 2.
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SBIT(ADCI, 0xD8, 7); // ADC Interrupt Bit.
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SBIT(DMA, 0xD8, 6); // DMA Mode Enable Bit.
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SBIT(CCONV, 0xD8, 5); // Continuous Conversion Bit.
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SBIT(SCONV, 0xD8, 4); // Single Conversion Bit.
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SBIT(CS3, 0xD8, 3); // Channel Selection Bit 4.
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SBIT(CS2, 0xD8, 2); // Channel Selection Bit 3.
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SBIT(CS1, 0xD8, 1); // Channel Selection Bit 2.
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SBIT(CS0, 0xD8, 0); // Channel Selection Bit 1.
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SFR(ADCCON3, 0xF5); //ADC Control SFR 3
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#define BUSY 0x80 // ADC Busy Status Bit.
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#define AVGS1 0x20 // Number of Average Selection Bit 2.
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#define AVGS0 0x10 // Number of Average Selection Bit 1.
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#define TYPICAL 0x02 // Calibration Type Select Bit.
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#define SCAL 0x01 // Start Calibration Cycle Bit.
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SFR(ADCDATAL, 0xD9); // ADC Result byte low.
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SFR(ADCDATAH, 0xDA); // ADC Result byte high. WARNING: bits 4 to 7 are the ADC channel!
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SFR(ADCOFSL, 0xF1); // Offset calibration coefficient byte (low).
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SFR(ADCOFSH, 0xF2); // Offset calibration coefficient byte (high).
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SFR(ADCGAINL, 0xF3); // Gain calibration coefficient byte (low).
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SFR(ADCGAINH, 0xF4); // Gain calibration coefficient byte (high).
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SFR(SPIDAT, 0xF7); // SPI Data Register.
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SFR(SPICON, 0xF8); // SPI Control Register.
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SBIT(ISPI, 0xF8, 7); // SPI Interrupt Bit.
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SBIT(WCOL, 0xF8, 6); // Write Collision Error Bit.
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SBIT(SPE, 0xF8, 5); // SPI Interface Enable Bit.
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SBIT(SPIM, 0xF8, 4); // SPI Master/Slave Mode Select Bit.
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SBIT(CPOL, 0xF8, 3); // Clock Polarity Select Bit.
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SBIT(CPHA, 0xF8, 2); // Clock Phase Select Bit.
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SBIT(SPR1, 0xF8, 1); // SPI Bit Rate Select Bit 2.
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SBIT(SPR0, 0xF8, 0); // SPI Bit Rate Select Bit 1.
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SFR(DAC0L, 0xF9); // DAC0 Data Low Byte.
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SFR(DAC0H, 0xFA); // DAC0 Data High Byte.
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SFR(DAC1L, 0xFB); // DAC1 Data Low Byte.
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SFR(DAC1H, 0xFC); // DAC1 Data High Byte.
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SFR(DACCON, 0xFD); // DAC Control Register.
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#define MODE 0x80 // 8/12 bit selection.
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#define RNG1 0x40 // DAC1 Range Select Bit.
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#define RNG0 0x20 // DAC0 Range Select Bit.
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#define CLR1 0x10 // DAC1 Clear Bit.
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#define CLR0 0x08 // DAC0 Clear Bit.
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#define SYNC 0x04 // DAC0/1 Update Synchronization Bit.
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#define PD1 0x02 // DAC1 Power-Down Bit.
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#define PD0 0x01 // DAC0 Power-Down Bit.
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#endif //REG_ADUC84X_H
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