352 lines
8.9 KiB
C
352 lines
8.9 KiB
C
/*--------------------------------------------------------------------------
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P89LPC932.H
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(English)
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This header allows to use the microcontroler Philips P89LPC932
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with the compiler SDCC.
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Copyright (c) 2005 Omar Espinosa--e-mail: opiedrahita2003 AT yahoo.com.
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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(Spanish-Español)
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Archivo encabezador para el ucontrolador Philips P89LPC932.
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Derechos de copy (DC) 2005. OMAR ESPINOSA P. E-mail: opiedrahita2003 AT yahoo.com
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Uso libre
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--------------------------------------------------------------------------*/
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#ifndef __REG932_H__
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#define __REG932_H__
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/* BYTE Registers */
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__sfr __at (0x80) P0 ;
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__sfr __at (0x90) P1 ;
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__sfr __at (0xA0) P2 ;
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__sfr __at (0xB0) P3 ;
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__sfr __at (0xD0) PSW ;
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__sfr __at (0xE0) ACC ;
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__sfr __at (0xF0) B ;
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__sfr __at (0x81) SP ;
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__sfr __at (0x82) DPL ;
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__sfr __at (0x83) DPH ;
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__sfr __at (0x87) PCON ;
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__sfr __at (0x88) TCON ;
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__sfr __at (0x89) TMOD ;
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__sfr __at (0x8A) TL0 ;
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__sfr __at (0x8B) TL1 ;
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__sfr __at (0x8C) TH0 ;
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__sfr __at (0x8D) TH1 ;
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__sfr __at (0xA8) IEN0 ;
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__sfr __at (0xB8) IP0 ;
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__sfr __at (0x98) SCON ;
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__sfr __at (0x99) SBUF ;
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__sfr __at (0xA2) AUXR1 ;
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__sfr __at (0xA9) SADDR ;
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__sfr __at (0xB9) SADEN ;
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__sfr __at (0xCC) TL2 ;
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__sfr __at (0xCD) TH2 ;
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__sfr __at (0xBE) BRGR0 ;
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__sfr __at (0xBF) BRGR1 ;
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__sfr __at (0xBD) BRGCON ;
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__sfr __at (0xEA) CCCRA ;
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__sfr __at (0xEB) CCCRB ;
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__sfr __at (0xEC) CCCRC ;
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__sfr __at (0xED) CCCRD ;
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__sfr __at (0xAC) CMP1 ;
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__sfr __at (0xAD) CMP2 ;
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__sfr __at (0xF1) DEECON ;
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__sfr __at (0xF2) DEEDAT ;
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__sfr __at (0xF3) DEEADR ;
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__sfr __at (0x95) DIVM ;
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__sfr __at (0xDB) I2ADR ;
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__sfr __at (0xD8) I2CON ;
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__sfr __at (0xDA) I2DAT ;
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__sfr __at (0xDD) I2SCLH ;
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__sfr __at (0xDC) I2SCLL ;
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__sfr __at (0xD9) I2STAT ;
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__sfr __at (0xAB) ICRAH ;
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__sfr __at (0xAA) ICRAL ;
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__sfr __at (0xAF) ICRBH ;
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__sfr __at (0xAE) ICRBL ;
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__sfr __at (0xE8) IEN1 ;
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__sfr __at (0xF8) IP1 ;
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__sfr __at (0xF7) IP1H ;
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__sfr __at (0x94) KBCON ;
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__sfr __at (0x86) KBMASK ;
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__sfr __at (0x93) KBPATN ;
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__sfr __at (0xEF) OCRAH ;
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__sfr __at (0xEE) OCRAL ;
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__sfr __at (0xFB) OCRBH ;
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__sfr __at (0xFA) OCRBL ;
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__sfr __at (0xFD) OCRCH ;
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__sfr __at (0xFC) OCRCL ;
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__sfr __at (0xFF) OCRDH ;
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__sfr __at (0xFE) OCRDL ;
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__sfr __at (0x84) P0M1 ;
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__sfr __at (0x85) P0M2 ;
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__sfr __at (0x91) P1M1 ;
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__sfr __at (0x92) P1M2 ;
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__sfr __at (0xA4) P2M1 ;
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__sfr __at (0xA5) P2M2 ;
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__sfr __at (0xB1) P3M1 ;
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__sfr __at (0xB2) P3M2 ;
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__sfr __at (0xB5) PCONA ;
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__sfr __at (0xF6) PT0AD ;
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__sfr __at (0xDF) RSTSRC ;
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__sfr __at (0xD1) RTCCON ;
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__sfr __at (0xD2) RTCH ;
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__sfr __at (0xD3) RTCL ;
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__sfr __at (0xBA) SSTAT ;
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__sfr __at (0xE2) SPCTL ;
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__sfr __at (0xE1) SPSTAT ;
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__sfr __at (0xE3) SPDAT ;
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__sfr __at (0x8F) TAMOD ;
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__sfr __at (0xC8) TCR20 ;
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__sfr __at (0xF9) TCR21 ;
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__sfr __at (0xC9) TICR2 ;
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__sfr __at (0xE9) TIFR2 ;
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__sfr __at (0xDE) TISE2 ;
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__sfr __at (0xCF) TOR2H ;
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__sfr __at (0xCE) TOR2L ;
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__sfr __at (0xCB) TPCR2H ;
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__sfr __at (0xCA) TPCR2L ;
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__sfr __at (0x96) TRIM ;
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__sfr __at (0xA7) WDCON ;
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__sfr __at (0xC1) WDL ;
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__sfr __at (0xC2) WFEED1 ;
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__sfr __at (0xC3) WFEED2 ;
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__sfr __at (0xB7) IP0H ;
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/* BIT Registers */
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/* PSW */
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__sbit __at (0xD7) PSW_7;
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__sbit __at (0xD6) PSW_6;
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__sbit __at (0xD5) PSW_5;
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__sbit __at (0xD4) PSW_4;
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__sbit __at (0xD3) PSW_3;
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__sbit __at (0xD2) PSW_2;
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__sbit __at (0xD1) PSW_1;
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__sbit __at (0xD0) PSW_0;
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#define CY PSW_7
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#define AC PSW_6
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#define F0 PSW_5
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#define RS1 PSW_4
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#define RS0 PSW_3
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#define OV PSW_2
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#define F1 PSW_1
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#define P PSW_0
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/* TCON */
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__sbit __at (0x8F) TCON_7;
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__sbit __at (0x8E) TCON_6;
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__sbit __at (0x8D) TCON_5;
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__sbit __at (0x8C) TCON_4;
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__sbit __at (0x8B) TCON_3;
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__sbit __at (0x8A) TCON_2;
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__sbit __at (0x89) TCON_1;
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__sbit __at (0x88) TCON_0;
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#define TF1 TCON_7
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#define TR1 TCON_6
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#define TF0 TCON_5
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#define TR0 TCON_4
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#define IE1 TCON_3
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#define IT1 TCON_2
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#define IE0 TCON_1
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#define IT0 TCON_0
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/* IEN0 */
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__sbit __at (0xAF) IEN0_7;
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__sbit __at (0xAE) IEN0_6;
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__sbit __at (0xAD) IEN0_5;
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__sbit __at (0xAC) IEN0_4; // alternatively "ESR"
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__sbit __at (0xAC) IEN0_4;
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__sbit __at (0xAB) IEN0_3;
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__sbit __at (0xAA) IEN0_2;
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__sbit __at (0xA9) IEN0_1;
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__sbit __at (0xA8) IEN0_0;
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#define EA IEN0_7
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#define EWDRT IEN0_6
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#define EBO IEN0_5
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#define ES IEN0_4 // alternatively "ESR"
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#define ESR IEN0_4
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#define ET1 IEN0_3
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#define EX1 IEN0_2
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#define ET0 IEN0_1
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#define EX0 IEN0_0
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/* IEN1 */
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__sbit __at (0xEF) IEN1_7;
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__sbit __at (0xEE) IEN1_6;
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__sbit __at (0xEC) IEN1_4;
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__sbit __at (0xEB) IEN1_3;
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__sbit __at (0xEA) IEN1_2;
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__sbit __at (0xE9) IEN1_1;
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__sbit __at (0xE8) IEN1_0;
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#define EIEE IEN1_7
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#define EST IEN1_6
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#define ECCU IEN1_4
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#define ESPI IEN1_3
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#define EC IEN1_2
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#define EKBI IEN1_1
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#define EI2C IEN1_0
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/* IP0 */
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__sbit __at (0xBE) IP0_6;
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__sbit __at (0xBD) IP0_5;
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__sbit __at (0xBC) IP0_4; // alternatively "PSR"
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__sbit __at (0xBC) IP0_4;
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__sbit __at (0xBB) IP0_3;
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__sbit __at (0xBA) IP0_2;
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__sbit __at (0xB9) IP0_1;
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__sbit __at (0xB8) IP0_0;
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#define PWDRT IP0_6
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#define PB0 IP0_5
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#define PS IP0_4 // alternatively "PSR"
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#define PSR IP0_4
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#define PT1 IP0_3
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#define PX1 IP0_2
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#define PT0 IP0_1
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#define PX0 IP0_0
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/* SCON */
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__sbit __at (0x9F) SCON_7; // alternatively "FE"
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__sbit __at (0x9E) SCON_6;
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__sbit __at (0x9D) SCON_5;
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__sbit __at (0x9C) SCON_4;
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__sbit __at (0x9B) SCON_3;
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__sbit __at (0x9A) SCON_2;
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__sbit __at (0x99) SCON_1;
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__sbit __at (0x98) SCON_0;
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#define SM0 SCON_7 // alternatively "FE"
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#define FE SCON_7
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#define SM1 SCON_6
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#define SM2 SCON_5
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#define REN SCON_4
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#define TB8 SCON_3
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#define RB8 SCON_2
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#define TI SCON_1
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#define RI SCON_0
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/* I2CON */
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__sbit __at (0xDE) I2CON_6;
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__sbit __at (0xDD) I2CON_5;
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__sbit __at (0xDC) I2CON_4;
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__sbit __at (0xDB) I2CON_3;
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__sbit __at (0xDA) I2CON_2;
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__sbit __at (0xD8) I2CON_0;
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#define I2EN I2CON_6;
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#define STA I2CON_5;
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#define STO I2CON_4;
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#define SI I2CON_3;
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#define AA I2CON_2;
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#define CRSEL I2CON_0;
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/* P0 */
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__sbit __at (0x87) P0_7;
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__sbit __at (0x86) P0_6; // alternatively "CMP1"
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__sbit __at (0x85) P0_5;
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__sbit __at (0x84) P0_4;
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__sbit __at (0x83) P0_3;
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__sbit __at (0x82) P0_2;
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__sbit __at (0x81) P0_1;
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__sbit __at (0x80) P0_0; // alternatively "CMP2"
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#define KB7 P0_7 // alternatively "T1"
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#define T1 P0_7
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#define KB6 P0_6 // alternatively "CMP_1"
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#define CMP_1 P0_6
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#define KB5 P0_5
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#define KB4 P0_4
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#define KB3 P0_3
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#define KB2 P0_2
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#define KB1 P0_1
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#define KB0 P0_0 // alternatively "CMP_2"
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#define CMP_2 P0_0
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/* P1 */
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__sbit __at (0x97) P1_7;
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__sbit __at (0x96) P1_6;
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__sbit __at (0x95) P1_5;
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__sbit __at (0x94) P1_4;
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__sbit __at (0x93) P1_3;
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__sbit __at (0x92) P1_2;
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__sbit __at (0x91) P1_1;
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__sbit __at (0x90) P1_0;
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#define OCC P1_7
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#define OCB P1_6
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#define RST P1_5
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#define INT1 P1_4
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#define INT0 P1_3 // alternatively "SDA"
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#define SDA P1_3
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#define T0 P1_2 // alternatively "SCL"
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#define SCL P1_2
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#define RxD P1_1
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#define TxD P1_0
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/* P2 */
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__sbit __at (0xA7) P2_7;
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__sbit __at (0xA6) P2_6;
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__sbit __at (0xA5) P2_5;
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__sbit __at (0xA4) P2_4;
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__sbit __at (0xA3) P2_3;
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__sbit __at (0xA2) P2_2;
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__sbit __at (0xA1) P2_1;
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__sbit __at (0xA0) P2_0;
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#define ICA P2_7
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#define OCA P2_6
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#define SPICLK P2_5
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#define SS P2_4
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#define MISO P2_3
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#define MOSI P2_2
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#define OCD P2_1
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#define ICB P2_0
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/* P3 */
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__sbit __at (0xB1) P3_1;
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__sbit __at (0xB0) P3_0;
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#define XTAL1 P3_1
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#define XTAL2 P3_0
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/* TCR20 */
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__sbit __at (0xCF) TCR20_7;
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__sbit __at (0xCE) TCR20_6;
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__sbit __at (0xCD) TCR20_5;
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__sbit __at (0xCC) TCR20_4;
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__sbit __at (0xCB) TCR20_3;
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__sbit __at (0xCA) TCR20_2;
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__sbit __at (0xC9) TCR20_1;
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__sbit __at (0xC8) TCR20_0;
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#define PLLEN TCR20_7
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#define HLTRN TCR20_6
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#define HLTEN TCR20_5
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#define ALTCD TCR20_4
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#define ALTAB TCR20_3
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#define TDIR2 TCR20_2
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#define TMOD21 TCR20_1
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#define TMOD20 TCR20_0
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#endif
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