258 lines
11 KiB
C
258 lines
11 KiB
C
/*-------------------------------------------------------------------------
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at89c51ed2.h: Register Declarations for the Atmel AT89C51RD2/ED2 Processor
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Copyright (C) 2005, Jesus Calvino-Fraga / jesusc at ece.ubc.ca
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This library is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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Free Software Foundation; either version 2, or (at your option) any
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later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this library; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
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MA 02110-1301, USA.
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As a special exception, if you link this library with other files,
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some of which are compiled with SDCC, to produce an executable,
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this library does not by itself cause the resulting executable to
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be covered by the GNU General Public License. This exception does
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not however invalidate any other reasons why the executable file
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might be covered by the GNU General Public License.
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-------------------------------------------------------------------------*/
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#ifndef REG_AT89C51ED2_H
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#define REG_AT89C51ED2_H
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#include <8052.h> // Load definitions for the 8052
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#ifdef REG8052_H
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#undef REG8052_H
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#endif
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// Define AT89C51RD2/ED2 specific registers only
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__sfr __at (0x8E) AUXR; //Auxiliary function register
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#define DPU 0x80 //'1'=Disables weak pull-up
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#define M0 0x20 //'1'=Strechs MOVX control signals
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#define XRS2 0x10 // XRAM select bit 2
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#define XRS1 0x08 // XRAM select bit 1
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#define XRS0 0x04 // XRAM select bit 0
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// XRS2 XRS1 XRS2 XRAM Size
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// 0 0 0 256 bytes
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// 0 0 1 512 bytes
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// 0 1 0 768 bytes (default)
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// 0 1 1 1024 bytes
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// 1 0 0 1792 bytes
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#define EXTRAM 0x02 //'0'=uses internal XRAM.
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#define AO 0x01 //'1'=Disables ALE generation.
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__sfr __at (0xA2) AUXR1; //Auxiliary function register 1
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#define ENBOOT 0x20 //'0'=Disables boot ROM
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#define GF3 0x08 //General purpose user-defined flag.
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#define DPS 0x01 //Data pointer select.
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__sfr __at (0x97) CKRL; //Clock Reload Register
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__sfr __at (0x8F) CKCON0; //Clock control Register 0
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#define WDTX2 0x40 //Watch Dog Clock speed '1'=12 ck/cy, '0'=6 ck/cy
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#define PCAX2 0x20 //Programmable Counter Array Clock speed '1'=12 ck/cy, '0'=6 ck/cy
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#define SIX2 0x10 //Enhanced UART Clock (Mode 0 and 2) speed '1'=12 ck/cy, '0'=6 ck/cy
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#define T2X2 0x08 //Timer2 Clock speed '1'=12 ck/cy, '0'=6 ck/cy
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#define T1X2 0x04 //Timer1 Clock speed '1'=12 ck/cy, '0'=6 ck/cy
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#define T0X2 0x02 //Timer0 Clock speed '1'=12 ck/cy, '0'=6 ck/cy
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#define X2 0x01 //CPU Clock '0'=12 ck/cy, '1'=6 ck/cy
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__sfr __at (0xAF) CKCON1; //Clock control Register 1
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#define XPIX2 0x01 //SPI Clock speed '1'=12 ck/cy, '0'=6 ck/cy
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__sfr __at (0xFA) CCAP0H; //Module 0 Capture HIGH.
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__sfr __at (0xFB) CCAP1H; //Module 1 Capture HIGH.
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__sfr __at (0xFC) CCAP2H; //Module 2 Capture HIGH.
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__sfr __at (0xFD) CCAP3H; //Module 3 Capture HIGH.
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__sfr __at (0xFE) CCAP4H; //Module 4 Capture HIGH.
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__sfr __at (0xEA) CCAP0L; //Module 0 Capture LOW.
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__sfr __at (0xEB) CCAP1L; //Module 1 Capture LOW.
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__sfr __at (0xEC) CCAP2L; //Module 2 Capture LOW.
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__sfr __at (0xED) CCAP3L; //Module 3 Capture LOW.
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__sfr __at (0xEE) CCAP4L; //Module 4 Capture LOW.
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__sfr __at (0xDA) CCAPM0; //Module 0 Mode.
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__sfr __at (0xDB) CCAPM1; //Module 1 Mode.
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__sfr __at (0xDC) CCAPM2; //Module 2 Mode.
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__sfr __at (0xDD) CCAPM3; //Module 3 Mode.
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__sfr __at (0xDE) CCAPM4; //Module 4 Mode.
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//The preceding five registers have the following bits:
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#define ECOM 0x40 //Enable Comparator.
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#define CAPP 0x20 //1=enables positive edge capture.
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#define CAPN 0x10 //1=enables negative edge capture.
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#define MAT 0x08 //When counter matches sets CCF_n bit causing and interrupt.
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#define TOG 0x04 //Toggle output on match.
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#define PWM 0x02 //Pulse width modulation mode.
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#define ECCF 0x01 //Enable CCF interrupt.
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__sfr __at (0xD8) CCON; //PCA Counter Control
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__sbit __at (0xDF) CF; //PCA Counter overflow flag.
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__sbit __at (0xDE) CR ; //PCA Counter Run Control Bit. 1=counter on. 0=counter off.
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__sbit __at (0xDC) CCF4;//PCA Module 4 Interrupt Flag.
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__sbit __at (0xDB) CCF3;//PCA Module 3 Interrupt Flag.
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__sbit __at (0xDA) CCF2;//PCA Module 2 Interrupt Flag.
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__sbit __at (0xD9) CCF1;//PCA Module 1 Interrupt Flag.
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__sbit __at (0xD8) CCF0;//PCA Module 0 Interrupt Flag.
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__sfr __at (0xF9) CH; //PCA Counter HIGH.
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__sfr __at (0xE9) CL; //PCA Counter LOW.
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__sfr __at (0xD9) CMOD; //PCA Counter Mode.
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#define CIDL 0x80 //CIDL=0 program the PCA counter to work during idle mode.
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#define WDTE 0x40 //Watchdog Timer Enable.
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#define CPS1 0x04 //PCA Count Pulse Select bit 1.
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#define CPS0 0x02 //PCA Count Pulse Select bit 0.
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//00=Internal clock, Fosc/6
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//01=Internal clock, Fosc/6
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//10=Timer 0 overflow
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//11=External clock at ECI/P1.2 pin (max rate=Fosc/4)
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#define ECF 0x01 //PCA Enable Counter Overflow Interrupt.
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//Attention IEN0 is the same as register IE found in <8051.h> only bit EC added here.
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__sfr __at (0xA8) IEN0; //Interrupt Enable 1.
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__sbit __at (0xAE) EC; //PCA Interrupt Enable bit.
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__sfr __at (0xB1) IEN1; //Interrupt Enable 1
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#define ESPI 0x04 //SPA Interrupt Enable bit.
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#define KBD 0x01 //Keyboard Interrupt Enable bit.
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//Attention IPL0 is the same as register IP found in <8051.h>
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__sfr __at (0xB8) IPL0; //Interrupt Priority 0 LOW
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__sbit __at (0xBE) PPCL;//PCA Interrupt Priority low bit.
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__sbit __at (0xBD) PT2L;//Timer 2 Interrupt Priority Low Bit.
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__sbit __at (0xBC) PSL; //Serial Port Interrupt Priority Low Bit.
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__sbit __at (0xBB) PT1L;//Timer 1 Interrupt Priority Low Bit.
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__sbit __at (0xBA) PX1L;//External Interrupt 1 Priority Low Bit.
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__sbit __at (0xB9) PT0L;//Timer 0 Interrupt Priority Low Bit.
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__sbit __at (0xB8) PX0L;//External Interrupt 0 Priority Low Bit.
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__sfr __at (0xB7) IPH0; //Interrupt Priority 0 HIGH
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#define PPCH 0x40 //PCA Interrupt Priority High Bit.
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#define PT2H 0x20 //Timer 2 Interrupt Priority High Bit.
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#define PSH 0x10 //Serial Port Interrupt Priority High Bit.
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#define PT1H 0x08 //Timer 1 Interrupt Priority High Bit.
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#define PX1H 0x04 //External Interrupt 1 Priority High Bit.
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#define PT0H 0x02 //Timer 0 Interrupt Priority High Bit.
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#define PX0H 0x01 //External Interrupt 0 Priority High Bit.
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__sfr __at (0xB2) IPL1; //Interrupt Priority 1 LOW.
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#define SPIL 0x04 //SPI Priority Low Bit
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#define KBDL 0x01 //Keyboard Priority Low Bit
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__sfr __at (0xB3) IPH1; //Interrupt Priority 1 HIGH.
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#define SPIH 0x04 //SPI Priority High Bit
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#define KBDH 0x01 //Keyboard Priority High Bit
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__sfr __at (0xC0) P4; //8-bit port 4
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__sbit __at (0xC0) P4_0 ;
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__sbit __at (0xC1) P4_1 ;
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__sbit __at (0xC2) P4_2 ;
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__sbit __at (0xC3) P4_3 ;
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__sbit __at (0xC4) P4_4 ;
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__sbit __at (0xC5) P4_5 ;
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__sbit __at (0xC6) P4_6 ;
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__sbit __at (0xC7) P4_7 ;
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// S. Qu 12/30/2008 4:23PM
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__sfr __at (0xE8) P5; //8-bit port 5
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__sbit __at (0xE8) P5_0 ;
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__sbit __at (0xE9) P5_1 ;
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__sbit __at (0xEA) P5_2 ;
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__sbit __at (0xEB) P5_3 ;
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__sbit __at (0xEC) P5_4 ;
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__sbit __at (0xED) P5_5 ;
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__sbit __at (0xEE) P5_6 ;
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__sbit __at (0xEF) P5_7 ;
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__sfr __at (0xA6) WDTRST; //WatchDog Timer Reset
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__sfr __at (0xA7) WDTPRG; //WatchDog Timer Program
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#define WTO2 0x04 //WDT Time-out select bit 2
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#define WTO1 0x02 //WDT Time-out select bit 1
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#define WTO0 0x01 //WDT Time-out select bit 0
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//This names appear also in the datasheet:
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#define S2 0x04 //WDT Time-out select bit 2
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#define S1 0x02 //WDT Time-out select bit 1
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#define S0 0x01 //WDT Time-out select bit 0
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//S2 S1 S0 Selected Time-out
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//0 0 0 (2^14 - 1) machine cycles, 16.3 ms @ FOSCA=12 MHz
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//0 0 1 (2^15 - 1) machine cycles, 32.7 ms @ FOSCA=12 MHz
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//0 1 0 (2^16 - 1) machine cycles, 65.5 ms @ FOSCA=12 MHz
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//0 1 1 (2^17 - 1) machine cycles, 131 ms @ FOSCA=12 MHz
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//1 0 0 (2^18 - 1) machine cycles, 262 ms @ FOSCA=12 MHz
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//1 0 1 (2^19 - 1) machine cycles, 542 ms @ FOSCA=12 MHz
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//1 1 0 (2^20 - 1) machine cycles, 1.05 s @ FOSCA=12 MHz
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//1 1 1 (2^21 - 1) machine cycles, 2.09 s @ FOSCA=12 MHz
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__sfr __at (0xA9) SADDR; //Serial Port Address Register.
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__sfr __at (0xB9) SADEN; //Serial Port Address Enable.
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__sfr __at (0xC3) SPCON; //SPI Control Register
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#define SPR2 0x80 //SPI Clork Rate select bit 2.
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#define SPEN 0x40 //SPI enable bit. When set enables SPI.
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#define SSDIS 0x20 //Cleared to enable SS in both Master and Slave modes.
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#define MSTR 0x10 //1=master mode. 0=slave mode.
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#define CPOL 0x08 //1=SCK is high when idle (active low), 0=SCK is low when idle (active high).
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#define CPHA 0x04 //1=shift triggered on the trailing edge of SCK. 0=shift trig. on leading edge.
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#define SPR1 0x02 //SPI Clork Rate select bit 1.
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#define SPR0 0x01 //SPI Clork Rate select bit 0.
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//SPR2 SPR1 SPR0 Baud Rate Divisor
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// 0 0 0 2
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// 0 0 1 4
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// 0 1 0 8
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// 0 1 1 16
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// 1 0 0 32
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// 1 0 1 64
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// 1 1 0 128
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// 1 1 1 Invalid: Don't Use
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__sfr __at (0xC4) SPSTA; //Serial Peripheral Status register
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#define SPIF 0x80 //Serial Peripheral Data Transfer Flag
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#define WCOL 0x40 //Write collision Flag.
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#define SSERR 0x20 //Synchronous Serial Slave Error Flag
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#define MODF 0x10 //Mode Fault Flag
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__sfr __at (0xC5) SPDAT; //SPI Data
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__sfr __at (0xC9) T2MOD; //Timer 2 mode control
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#define T2OE 0x02 //Timer 2 Output Enable bit.
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#define DCEN 0x01 //Down count enable
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__sfr __at (0x9B) BDRCON; //Baud Rate Control
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#define BRR 0x10 //Baud Rate Run Control bit. '1'=enable
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#define TBCK 0x08 //Transmission Baud rate Generator Selection bit for UART
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#define RBCK 0x04 //Reception Baud Rate Generator Selection bit for UART
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#define SPD 0x02 //Baud Rate Speed Control bit for UART
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#define SRC 0x01 //Baud Rate Source select bit in Mode 0 for UART
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__sfr __at (0x9A) BRL; //Baud Rate Reload
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__sfr __at (0x9C) KBLS; //Keyboard level Selector
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__sfr __at (0x9D) KBE; //Keyboard Input Enable
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__sfr __at (0x9E) KBF; //Keyboard Flag Register
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__sfr __at (0xD2) EECON; //EEPROM Data Control
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#define EEE 0x02 //EEPROM Enable. '1'=use EEPROM, '0'=use XRAM
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#define EEBUSY 0x01 //EEPROM Busy. '1'=EEPROM is busy programming
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// PCON bit definitions
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#define SMOD1 0x80
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#define SMOD0 0x40
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#define POF 0x10
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/* Interrupt numbers: address = (number * 8) + 3 */
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#define TF2_VECTOR 5 /* 0x2b timer 2 */
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#define PCA_VECTOR 6 /* 0x33 Programmable Counter Array */
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#define KBD_VECTOR 7 /* 0x3b Keyboard Interface */
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#define SPI_VECTOR 9 /* 0x4b Serial Port Interface */
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#endif /*REG_AT89C51ED2_H*/
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