70 lines
3.2 KiB
C
70 lines
3.2 KiB
C
/*-------------------------------------------------------------------------
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at89c51id2.h: Register Declarations for the Atmel AT89C51ID2 Processor
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Copyright (C) 2014, Victor Munoz / victor at munoz.name
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This library is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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Free Software Foundation; either version 2, or (at your option) any
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later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this library; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
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MA 02110-1301, USA.
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As a special exception, if you link this library with other files,
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some of which are compiled with SDCC, to produce an executable,
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this library does not by itself cause the resulting executable to
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be covered by the GNU General Public License. This exception does
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not however invalidate any other reasons why the executable file
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might be covered by the GNU General Public License.
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-------------------------------------------------------------------------*/
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#ifndef REG_AT89C51ID2_H
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#define REG_AT89C51ID2_H
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#include <at89c51ed2.h> // Load definitions for the at89c51ed2.h
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//Clock control Register 0 CKCON0(0x8F) additional definitions
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#define TWIX2 0x80 // 2-wire clock (CPU clock X2 only) '1'=12 ck/cy, '0'=6 ck/cy
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// Two wire interface control registers
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__sfr __at (0x93) SSCON; // Synchronous Serial Control register (93h)
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#define CR2 0x80 // Control Rate bit 2
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#define SSIE 0x40 // Synchronous Serial Interface Enable bit
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#define STA 0x20 // Start flag
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#define STO 0x10 // Stop flag
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#define SI 0x08 // Synchronous Serial Interrupt flag
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#define AA 0x04 // Assert Acknowledge flag
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#define CR1 0x02 // Control Rate bit 1
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#define CR0 0x01 // Control Rate bit 0
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__sfr __at (0x94) SSCS; // Synchronous Serial Control and Status Register (read) (094h)
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#define SC4 0x80 // Status Code bit 4
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#define SC3 0x40 // Status Code bit 3
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#define SC2 0x20 // Status Code bit 2
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#define SC1 0x10 // Status Code bit 1
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#define SC0 0x08 // Status Code bit 0
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__sfr __at (0x95) SSDAT; // Synchronous Serial Data register (read/write) (095h)
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__sfr __at (0x96) SSADR; // Synchronous Serial Address Register (read/write) (096h)
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#define GC 0x01 // General Call bit
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//Interrupt Enable 1 IEN1(0xB1) additional definitions
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#define ETWI 0x02 // Two Wire Interrupt Enable bit.
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//Interrupt Priority 1 LOW IPL1(0xB2) additional definitions
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#define TWIL 0x02
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//Interrupt Priority 1 HIGH IPH1(0xB3) additional definitions
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#define TWIH 0x02
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/* Interrupt numbers: address = (number * 8) + 3 */
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#define TWI_VECTOR 8 /* 0x43 Two wire interface */
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#endif /*REG_AT89C51ID2_H*/
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