93 lines
4.1 KiB
C
93 lines
4.1 KiB
C
/*-------------------------------------------------------------------------
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at89s53.h - Register Declarations for the Atmel AT89S53 Processor
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Copyright (C) 2005, Jesus Calvino-Fraga / jesusc at ece.ubc.ca
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This library is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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Free Software Foundation; either version 2, or (at your option) any
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later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this library; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
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MA 02110-1301, USA.
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As a special exception, if you link this library with other files,
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some of which are compiled with SDCC, to produce an executable,
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this library does not by itself cause the resulting executable to
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be covered by the GNU General Public License. This exception does
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not however invalidate any other reasons why the executable file
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might be covered by the GNU General Public License.
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-------------------------------------------------------------------------*/
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#ifndef REG_AT89S53_H
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#define REG_AT89S53_H
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#include <8052.h> /* load difinitions for the 8052 core */
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#ifdef REG8052_H
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#undef REG8052_H
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#endif
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/* define AT89S53 specific registers only */
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__sfr __at (0x84) DP1L; /* Data Pointer 1 Low Byte */
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__sfr __at (0x85) DP1H; /* Data Pointer 1 High Byte */
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__sfr __at (0x86) SPDR; /* SPI Data Register */
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__sfr __at (0xAA) SPSR; /* SPI Status Register */
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__sfr __at (0x96) WMCON; /* Watchdog and Memory Control Register */
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__sfr __at (0xD5) SPCR; /* SPI Control Register */
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/*------------------------------------------------
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SPSR (0xAA) Bit Values - Reset Value = 0000.0000
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------------------------------------------------*/
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#define WCOL_ 0x40 /* SPI Write Collision Flag: 1=Collision */
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#define SPIF_ 0x80 /* SPI Interrupt Flag */
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/*------------------------------------------------
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WMCON (0x96) Bit Values
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------------------------------------------------*/
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#define WDTEN_ 0x01
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#define WDTRST_ 0x02 /* Watchdog Timer Reset and EEPROM Ready,/Busy Flag*/
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#define EERDY_ 0x02 /* Watchdog Timer Reset and EEPROM Ready,/Busy Flag */
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#define DPS_ 0x04 /* Data Pointer Select: 0=DP0, 1=DP1 */
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#define EEMEN_ 0x08 /* Internal EEPROM Access Enable: 1=Enabled */
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#define EEMWE_ 0x10 /* Internal EEPROM Write Enable: 1=Enabled */
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#define PS0_ 0x20 /* Prescaler bit 0 for the Watchdog Timer */
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#define PS1_ 0x40 /* Prescaler bit 1 for the Watchdog Timer */
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#define PS2_ 0x80 /* Prescaler bit 2 for the Watchdog Timer */
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/* 000 = 16ms Timeout */
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/* 001 = 32ms Timeout */
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/* 010 = 64ms Timeout */
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/* 011 = 128ms Timeout */
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/* 100 = 256ms Timeout */
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/* 101 = 512ms Timeout */
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/* 110 = 1024ms Timeout */
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/* 111 = 2048ms Timeout */
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/*------------------------------------------------
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SPCR (0xD5) Bit Values - Reset Value = 0000.01XX
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------------------------------------------------*/
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#define SPR0_ 0x01 /* SPI Clock Rate Select bit 0 */
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#define SPR1_ 0x02 /* SPI Clock Rate Select bit 1 */
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/* 00 = Fosc / 4 */
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/* 01 = Fosc / 16 */
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/* 10 = Fosc / 64 */
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/* 11 = Fosc / 128 */
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#define CPHA_ 0x04 /* SPI Clock Phase */
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#define CPOL_ 0x08 /* SPI Clock Polarity */
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#define MSTR_ 0x10 /* SPI Master/Slave Select: 0=Slave, 1=Master */
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#define DORD_ 0x20 /* SPI Data Order: 0=MSB First, 1=LSB First */
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#define SPE_ 0x40 /* SPI Enable: 0=Disabled, 1=Enabled */
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#define SPIE_ 0x80 /* SPI Interrupt Enable: 0=Disabled, 1=Enabled */
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#endif /*REG_AT89S53_H*/
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