596 lines
30 KiB
C
596 lines
30 KiB
C
/*-------------------------------------------------------------------------
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uPSD33xx.h - Register Declarations for ST's uPSD33xx "Fast 8032 MCU with
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Programmable Logic"
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(Based on preliminary datasheet from Jan/2005 )
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Copyright (C) 2007, Jesus Calvino-Fraga / jesusc at ece.ubc.ca
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This library is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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Free Software Foundation; either version 2, or (at your option) any
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later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this library; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
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MA 02110-1301, USA.
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As a special exception, if you link this library with other files,
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some of which are compiled with SDCC, to produce an executable,
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this library does not by itself cause the resulting executable to
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be covered by the GNU General Public License. This exception does
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not however invalidate any other reasons why the executable file
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might be covered by the GNU General Public License.
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-------------------------------------------------------------------------*/
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#ifndef REG_UPSD33XX_H
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#define REG_UPSD33XX_H
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#include <compiler.h>
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//Interrupt vector numbers (see table 16 on datasheet)
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#define EXT0_INTERRUPT ((0x03-3)/8)
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#define TIMER0_INTERRUPT ((0x0B-3)/8)
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#define EXT1_INTERRUPT ((0x13-3)/8)
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#define TIMER1_INTERRUPT ((0x1B-3)/8)
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#define UART0_INTERRUPT ((0x23-3)/8)
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#define TIMER2_INTERRUPT ((0x2B-3)/8)
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#define TX2_INTERRUPT ((0x2B-3)/8)
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#define SPI_INTERRUPT ((0x53-3)/8)
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#define I2C_INTERRUPT ((0x43-3)/8)
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#define ADC_INTERRUPT ((0x3B-3)/8)
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#define PCA_INTERRUPT ((0x5B-3)/8)
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#define UART1_INTERRUPT ((0x4B-3)/8)
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SFR(SP, 0x81); // Stack Pointer.
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SFR(DPL, 0x82); // Data Pointer Low.
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SFR(DPH, 0x83); // Data Pointer High.
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SFR(DPTC, 0x85); // Data Pointer Control Register.
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SFR(DPS, 0x85); // Data Pointer Control Register alias for SDCC
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#define AT 0x40 //0:Manually Select Data Pointer / 1:Auto Toggle between DPTR0 and DPTR1
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#define DPSE0 0x01 // 0:DPTR0 Selected for use as DPTR / 1:DPTR1 Selected for use as DPTR
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SFR(DPTM, 0x86); // Data Pointer Mode Register.
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#define DP1_1 0x08 // DPTR1 Mode Bit 1.
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#define DP1_0 0x04 // DPTR1 Mode Bit 0.
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#define DP0_1 0x02 // DPTR0 Mode Bit 1.
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#define DP0_0 0x01 // DPTR0 Mode Bit 0.
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// DPx_1 DPx_0
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// 0 0 : DPTRx No Change
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// 0 1 : Reserved
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// 1 0 : DPTRx Auto Increment
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// 1 1 : DPTRx Auto Decrement
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SFR(PCON, 0x87); // Power Control.
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#define SMOD0 0x80 //Baud Rate Double Bit (UART0)
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#define SMOD1 0x40 //Baud Rate Double Bit (UART1)
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#define POR 0x10 //Only a power-on reset sets this bit (cold reset).
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#define RCLK1 0x08 //Receive Clock Flag (UART1)
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#define TCLK1 0x04 //Transmit Clock Flag (UART1)
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#define PD 0x02 //Power-Down Mode Enable.
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#define IDL 0x01 //Idle Mode Enable.
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SFR(TCON, 0x88); // Timer/Counter Control.
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SBIT(TF1, 0x88, 7); // Timer 1 overflow flag.
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SBIT(TR1, 0x88, 6); // Timer 1 run control flag.
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SBIT(TF0, 0x88, 5); // Timer 0 overflow flag.
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SBIT(TR0, 0x88, 4); // Timer 0 run control flag.
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SBIT(IE1, 0x88, 3); // Interrupt 1 flag.
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SBIT(IT1, 0x88, 2); // Interrupt 1 type control bit.
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SBIT(IE0, 0x88, 1); // Interrupt 0 flag.
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SBIT(IT0, 0x88, 0); // Interrupt 0 type control bit.
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SFR(TMOD, 0x89); // Timer/Counter Mode Control.
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#define GATE1 0x80 // External enable for timer 1.
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#define C_T1 0x40 // Timer or counter select for timer 1.
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#define M1_1 0x20 // Operation mode bit 1 for timer 1.
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#define M0_1 0x10 // Operation mode bit 0 for timer 1.
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#define GATE0 0x08 // External enable for timer 0.
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#define C_T0 0x04 // Timer or counter select for timer 0.
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#define M1_0 0x02 // Operation mode bit 1 for timer 0.
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#define M0_0 0x01 // Operation mode bit 0 for timer 0.
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SFR(TL0, 0x8A); // Timer 0 LSB.
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SFR(TL1, 0x8B); // Timer 1 LSB.
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SFR(TH0, 0x8C); // Timer 0 MSB.
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SFR(TH1, 0x8D); // Timer 1 MSB.
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//For P1SFS0 and P1SFS1 SFRs details check datasheet Table 31.
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SFR(P1SFS0, 0x8E); //Port 1 Special Function Select 0 Register.
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#define P1SF07 0x80
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#define P1SF06 0x40
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#define P1SF05 0x20
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#define P1SF04 0x10
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#define P1SF03 0x08
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#define P1SF02 0x04
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#define P1SF01 0x02
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#define P1SF00 0x01
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SFR(P1SFS1, 0x8F); //Port 1 Special Function Select 1 Register.
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#define P1SF17 0x80
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#define P1SF16 0x40
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#define P1SF15 0x20
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#define P1SF14 0x10
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#define P1SF13 0x08
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#define P1SF12 0x04
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#define P1SF11 0x02
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#define P1SF10 0x01
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SFR(P1, 0x90); // Port 1
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SBIT(P1_0, 0x90, 0); // Port 1 bit 0.
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SBIT(P1_1, 0x90, 1); // Port 1 bit 1.
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SBIT(P1_2, 0x90, 2); // Port 1 bit 2.
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SBIT(P1_3, 0x90, 3); // Port 1 bit 3.
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SBIT(P1_4, 0x90, 4); // Port 1 bit 4.
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SBIT(P1_5, 0x90, 5); // Port 1 bit 5.
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SBIT(P1_6, 0x90, 6); // Port 1 bit 6.
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SBIT(P1_7, 0x90, 7); // Port 1 bit 7.
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//Alternate names (from figure 3)
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SBIT(T2, 0x90, 0); //Input to Timer/Counter 2.
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SBIT(T2X, 0x90, 1); //Capture/reload trigger for Counter 2.
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SBIT(RXD1, 0x90, 2);
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SBIT(TXD1, 0x90, 3);
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SBIT(SPICLK, 0x90, 4);
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SBIT(SPIRXD, 0x90, 5);
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SBIT(SPITXD, 0x90, 6);
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SBIT(SPISEL, 0x90, 7);
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SFR(P3SFS, 0x91); // Port 3 Special Function Select Register
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#define P3SF7 0x80
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#define P3SF6 0x40
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#define P3SF5 0x20
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#define P3SF4 0x10
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#define P3SF3 0x08
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#define P3SF2 0x04
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#define P3SF1 0x02
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#define P3SF0 0x01
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//For P4SFS0 and P4SFS1 SFRs details check datasheet Table 34.
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SFR(P4SFS0, 0x92); //Port 4 Special Function Select 0 Register.
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#define P4SF07 0x80
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#define P4SF06 0x40
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#define P4SF05 0x20
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#define P4SF04 0x10
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#define P4SF03 0x08
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#define P4SF02 0x04
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#define P4SF01 0x02
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#define P4SF00 0x01
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SFR(P4SFS1, 0x93); //Port 4 Special Function Select 1 Register.
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#define P4SF17 0x80
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#define P4SF16 0x40
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#define P4SF15 0x20
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#define P4SF14 0x10
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#define P4SF13 0x08
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#define P4SF12 0x04
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#define P4SF11 0x02
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#define P4SF10 0x01
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SFR(ADCPS, 0x94); // ADC pre-scaller?
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#define ADCCE 0x08 // ADC Conversion Reference Clock Enable.
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//ADC Reference Clock PreScaler. Only three Prescaler values are allowed:
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#define ADCPS2 0x02 // Resulting ADC clock is fOSC.
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#define ADCPS1 0x01 // Resulting ADC clock is fOSC/2.
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#define ADCPS0 0x00 // Resulting ADC clock is fOSC/4.
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SFR(ADAT0, 0x95); // A/D result register (bits 0 to 7).
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SFR(ADAT1, 0x96); // A/D result register (bits 8 and 9).
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SFR(ACON, 0x97); // A/D control register.
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#define AINTF 0x80 // ADC Interrupt flag. This bit must be cleared with software.
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#define AINTEN 0x40 // ADC Interrupt Enable.
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#define ADEN 0x20 // ADC Enable Bit.
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#define ADS2 0x10 // Analog channel Select bit 3.
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#define ADS1 0x08 // Analog channel Select bit 2.
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#define ADS0 0x04 // Analog channel Select bit 1.
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#define ADST 0x02 // ADC Start Bit.
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#define ADSF 0x01 // ADC Status Bit.
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SFR(SCON, 0x98); // For compatibity with legacy code
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SFR(SCON0, 0x98); // Serial Port UART0 Control Register
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SBIT(SM0, 0x98, 7); // Serial Port Mode Bit 0.
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SBIT(SM1, 0x98, 6); // Serial Port Mode Bit 1.
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SBIT(SM2, 0x98, 5); // Serial Port Mode Bit 2.
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SBIT(REN, 0x98, 4); // Enables serial reception.
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SBIT(TB8, 0x98, 3); // The 9th data bit that will be transmitted in Modes 2 and 3.
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SBIT(RB8, 0x98, 2); // In Modes 2 and 3, the 9th data bit that was received.
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SBIT(TI, 0x98, 1); // Transmit interrupt flag.
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SBIT(RI, 0x98, 0); // Receive interrupt flag.
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SFR(SBUF, 0x99); // For compatibity with legacy code.
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SFR(SBUF0, 0x99); // Serial Port UART0 Data Buffer.
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SFR(BUSCON, 0x9D); // Bus Control Register.
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#define EPFQ 0x80 // Enable Pre-Fetch Queue.
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#define EBC 0x40 // Enable Branch Cache.
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#define WRW1 0x20 // WR Wait bit 2.
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#define WRW0 0x10 // WR Wait bit 1.
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#define RDW1 0x08 // RD Wait bit 2.
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#define RDW0 0x04 // RD Wait bit 1.
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#define CW1 0x02 // PSEN Wait bit 2.
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#define CW0 0x01 // PSEN Wait bit 1.
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SFR(PCACL0, 0xA2); // The low 8 bits of PCA 0 16-bit counter.
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SFR(PCACH0, 0xA3); // The high 8 bits of PCA 0 16-bit counter.
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SFR(PCACON0, 0xA4); // PCA 0 Control Register.
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SFR(PCASTA, 0xA5); // PCA 0 and PCA 1 Status Register.
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SFR(PCACL1, 0xBA); // The low 8 bits of PCA 1 16-bit counter.
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SFR(PCACH1, 0xBB); // The high 8 bits of PCA 1 16-bit counter.
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SFR(PCACON1, 0xBC); // PCA 1 Control Register.
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SFR(IEA, 0xA7); // Interrupt Enable Addition Register.
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#define EADC 0x80 // Enable ADC Interrupt.
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#define ESPI 0x40 // Enable SPI Interrupt.
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#define EPCA 0x20 // Enable Programmable Counter Array Interrupt.
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#define ES1 0x10 // Enable UART1 Interrupt.
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#define EI2C 0x02 // Enable I2C Interrupt.
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SFR(IE, 0xA8); // Interrupt Enable Register.
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SBIT(EA, 0xA8, 7); // Global disable bit.
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SBIT(ET2, 0xA8, 5); // Enable Timer 2 Interrupt.
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SBIT(ES0, 0xA8, 4); // Enable UART0 Interrupt.
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SBIT(ET1, 0xA8, 3); // Enable Timer 1 Interrupt.
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SBIT(EX1, 0xA8, 2); // Enable External Interrupt INT1.
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SBIT(ET0, 0xA8, 1); // Enable Timer 0 Interrupt.
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SBIT(EX0, 0xA8, 0); // Enable External Interrupt INT0.
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SFR(TCMMODE0, 0xA9); // TCM 0 Mode.
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SFR(TCMMODE1, 0xAA); // TCM 1 Mode.
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SFR(TCMMODE2, 0xAB); // TCM 2 Mode.
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SFR(TCMMODE3, 0xBD); // TCM 3 Mode.
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SFR(TCMMODE4, 0xBE); // TCM 4 Mode.
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SFR(TCMMODE5, 0xBF); // TCM 5 Mode.
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//These are the bits for the six SFRs above:
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#define EINTF 0x80 // Enable the interrupt flags (INTF) in the Status Register to generate an interrupt.
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#define E_COMP 0x40 // Enable the comparator when set.
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#define CAP_PE 0x20 // Enable Capture Mode, a positive edge on the CEXn pin.
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#define CAP_NE 0x20 // Enable Capture Mode, a negative edge on the CEXn pin.
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#define MATCH 0x08 // A match from the comparator sets the INTF bits in the Status Register.
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#define TOGGLE 0x04 // A match on the comparator results in a toggling output on CEXn pin.
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#define PWM1 0x02 // PWM mode bit 2.
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#define PWM0 0x01 // PWM mode bit 1.
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SFR(CAPCOML0, 0xAC); // Capture/Compare register low of TCM 0.
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SFR(CAPCOMH0, 0xAD); // Capture/Compare register High of TCM 0.
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SFR(CAPCOML1, 0xAF); // Capture/Compare register low of TCM 1.
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SFR(CAPCOMH1, 0xB1); // Capture/Compare register High of TCM 1.
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SFR(CAPCOML2, 0xB2); // Capture/Compare register low of TCM 2.
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SFR(CAPCOMH2, 0xB3); // Capture/Compare register High of TCM 2.
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SFR(CAPCOML3, 0xC1); // Capture/Compare register low of TCM 3.
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SFR(CAPCOMH3, 0xC2); // Capture/Compare register High of TCM 3.
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SFR(CAPCOML4, 0xC3); // Capture/Compare register low of TCM 4.
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SFR(CAPCOMH4, 0xC4); // Capture/Compare register High of TCM 4.
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SFR(CAPCOML5, 0xC5); // Capture/Compare register low of TCM 5.
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SFR(CAPCOMH5, 0xC6); // Capture/Compare register High of TCM 5.
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SFR(IPA, 0xB7); // Interrupt Priority Addition register.
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#define PADC 0x80 // ADC Interrupt priority level.
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#define PSPI 0x40 // SPI Interrupt priority level.
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#define PPCA 0x20 // PCA Interrupt level.
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#define PS1 0x10 // UART1 Interrupt priority.
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#define PI2C 0x02 // I2C Interrupt priority level.
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SFR(IP, 0xB8); // Interrupt Priority Register.
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SBIT(PT2, 0xB8, 5); // Timer 2 Interrupt priority level.
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SBIT(PS0, 0xB8, 4); // UART0 Interrupt priority level.
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SBIT(PT1, 0xB8, 3); // Timer 1 Interrupt priority level.
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SBIT(PX1, 0xB8, 2); // External Interrupt INT1 priority level.
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SBIT(PT0, 0xB8, 1); // Timer 0 Interrupt priority level.
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SBIT(PX0, 0xB8, 0); // External Interrupt INT0 priority level.
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SFR(WDTRST, 0xA6); // Watchdog Timer Reset Counter Register.
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SFR(WDTKEY, 0xAE); //Watchdog Timer Key Register.
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SFR(P3, 0xB0); // I/O Port 3 Register
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SBIT(P3_0, 0xB0, 0); // Port 3 bit 0.
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SBIT(P3_1, 0xB0, 1); // Port 3 bit 1.
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SBIT(P3_2, 0xB0, 2); // Port 3 bit 2.
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SBIT(P3_3, 0xB0, 3); // Port 3 bit 3.
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SBIT(P3_4, 0xB0, 4); // Port 3 bit 4.
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SBIT(P3_5, 0xB0, 5); // Port 3 bit 5.
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SBIT(P3_6, 0xB0, 6); // Port 3 bit 6.
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SBIT(P3_7, 0xB0, 7); // Port 3 bit 7.
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SFR(P4, 0xC0); // I/O Port 4 Register
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SBIT(P4_0, 0xC0, 0); // Port 4 bit 0.
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SBIT(P4_1, 0xC0, 1); // Port 4 bit 1.
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SBIT(P4_2, 0xC0, 2); // Port 4 bit 2.
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SBIT(P4_3, 0xC0, 3); // Port 4 bit 3.
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SBIT(P4_4, 0xC0, 4); // Port 4 bit 4.
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SBIT(P4_5, 0xC0, 5); // Port 4 bit 5.
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SBIT(P4_6, 0xC0, 6); // Port 4 bit 6.
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SBIT(P4_7, 0xC0, 7); // Port 4 bit 7.
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SFR(PWMF0, 0xB4); // PWM frequency register 0.
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SFR(PWMF1, 0xC7); // PWM frequency register 1.
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SFR(T2CON, 0xC8); // Timer / Counter 2 Control.
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SBIT(TF2, 0xC8, 7); // Timer 2 overflow flag.
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SBIT(EXF2, 0xC8, 6); // Timer 2 external flag.
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SBIT(RCLK, 0xC8, 5); // Receive clock flag.
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SBIT(TCLK, 0xC8, 4); // Transmit clock flag.
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SBIT(EXEN2, 0xC8, 3); // Timer 2 external enable flag.
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SBIT(TR2, 0xC8, 2); // Start/stop control for timer 2.
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SBIT(CNT2, 0xC8, 1); // Timer or coutner select.
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SBIT(CAP2, 0xC8, 0); // Capture/reload flag.
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SFR(RCAP2L, 0xCA); // Timer 2 Capture LSB.
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SFR(RCAP2H, 0xCB); // Timer 2 Capture MSB.
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SFR(TL2, 0xCC); // Timer 2 LSB.
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SFR(TH2, 0xCD); // Timer 2 MSB.
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SFR(IRDACON, 0xCE); //IrDA control register
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#define IRDAEN 0x40 // IrDA Enable bit
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#define PULSE 0x20 // IrDA Pulse Modulation Select. 0: 1.627us, 1: 3/16 bit time pulses.
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#define CDIV4 0x10 //Specify Clock Divider bit 5.
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#define CDIV3 0x08 //Specify Clock Divider bit 4.
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#define CDIV2 0x04 //Specify Clock Divider bit 3.
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#define CDIV1 0x02 //Specify Clock Divider bit 2.
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#define CDIV0 0x01 //Specify Clock Divider bit 1.
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SFR(CCON0, 0xF9); // Clock Control Register.
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#define DBGCE 0x10 // Debug Unit Breakpoint Comparator Enable.
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#define CPUAR 0x08 // Automatic MCU Clock Recovery.
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#define CPUPS2 0x04 // MCUCLK Pre-Scaler bit 3.
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#define CPUPS1 0x02 // MCUCLK Pre-Scaler bit 2.
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#define CPUPS0 0x01 // MCUCLK Pre-Scaler bit 1.
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SFR(CCON2, 0xFB); // Pre-scaler value for PCA0.
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#define PCA0CE 0x10 // PCA0 Clock Enable.
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#define PCA0PS3 0x08 // PCA0 Pre-Scaler bit 4.
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#define PCA0PS2 0x04 // PCA0 Pre-Scaler bit 3.
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#define PCA0PS1 0x02 // PCA0 Pre-Scaler bit 2.
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#define PCA0PS0 0x01 // PCA0 Pre-Scaler bit 1.
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SFR(CCON3, 0xFC); // Pre-scaler value for PCA1.
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#define PCA1CE 0x10 // PCA1 Clock Enable.
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#define PCA1PS3 0x08 // PCA1 Pre-Scaler bit 4.
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#define PCA1PS2 0x04 // PCA1 Pre-Scaler bit 3.
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#define PCA1PS1 0x02 // PCA1 Pre-Scaler bit 2.
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#define PCA1PS0 0x01 // PCA1 Pre-Scaler bit 1.
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SFR(SPICLKD, 0xD2); // SPI Prescaler (Clock Divider) Register.
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#define DIV128 0x80
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#define DIV64 0x40
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#define DIV32 0x20
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#define DIV16 0x10
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#define DIV8 0x08
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#define DIV4 0x04
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SFR(SPISTAT, 0xD3); // SPI Interface Status Register.
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#define BUSY 0x10 // SPI Busy.
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#define TEISF 0x08 // Transmission End Interrupt Source flag.
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#define RORISF 0x04 // Receive Overrun Interrupt Source flag.
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#define TISF 0x02 // Transfer Interrupt Source flag.
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#define RISF 0x01 // Receive Interrupt Source flag.
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SFR(SPITDR, 0xD4); // SPI transmit data register.
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SFR(SPIRDR, 0xD5); // SPI receive data register.
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SFR(SPICON0, 0xD6); // SPI Control Register 0.
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#define TE 0x40 // Transmitter Enable.
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#define RE 0x20 // Receiver Enable.
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#define SPIEN 0x10 // SPI Enable.
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#define SSEL 0x08 // Slave Selection.
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#define FLSB 0x04 // First LSB.
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#define SPO 0x02 // Sampling Polarity.
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SFR(SPICON1, 0xD7); // SPI Interface Control Register 1.
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#define TEIE 0x08 // Transmission End Interrupt Enable.
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#define RORIE 0x04 // Receive Overrun Interrupt Enable.
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#define TIE 0x02 // Transmission Interrupt Enable.
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#define RIE 0x01 // Reception Interrupt Enable.
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SFR(SCON1, 0x98); // Serial Port Control.
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SBIT(SM0, 0x98, 7); // Serial Port Mode Bit 0.
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SBIT(SM1, 0x98, 6); // Serial Port Mode Bit 1.
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SBIT(SM2, 0x98, 5); // Serial Port Mode Bit 2.
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SBIT(REN, 0x98, 4); // Enables serial reception.
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SBIT(TB8, 0x98, 3); // The 9th data bit that will be transmitted in Modes 2 and 3.
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SBIT(RB8, 0x98, 2); // In Modes 2 and 3, the 9th data bit that was received.
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SBIT(TI, 0x98, 1); // Transmit interrupt flag.
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SBIT(RI, 0x98, 0); // Receive interrupt flag.
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SFR(SBUF1, 0xD9); // Data buffer for UART1.
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SFR(S1SETUP, 0xDB); // I2C START Condition Sample Setup register.
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#define EN_SS 0x80 // Enable Sample Setup.
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#define SMPL_SET6 0x40 // Sample Setting bit 7.
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#define SMPL_SET5 0x20 // Sample Setting bit 6.
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#define SMPL_SET4 0x10 // Sample Setting bit 5.
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#define SMPL_SET3 0x08 // Sample Setting bit 4.
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#define SMPL_SET2 0x04 // Sample Setting bit 3.
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#define SMPL_SET1 0x02 // Sample Setting bit 2.
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#define SMPL_SET0 0x01 // Sample Setting bit 1.
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SFR(S1CON, 0xDC); // I2C Interface Control Register.
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#define CR2 0x80 // SCL clock frequency select bit 3.
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#define ENI1 0x40 // I2C Interface Enable.
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#define STA 0x20 // START flag.
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#define STO 0x10 // STOP flag.
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#define ADDR 0x08 // Slave mode address.
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#define AA 0x04 // Assert Acknowledge enable.
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#define CR1 0x02 // SCL clock frequency select bit 2.
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#define CR0 0x01 // SCL clock frequency select bit 1.
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SFR(S1STA, 0xDD); // I2C Interface Status Register.
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#define GC 0x80 // General Call flag.
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#define STOP 0x40 // STOP flag.
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#define INTR 0x20 // Interrupt flag.
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#define TX_MODE 0x10 // Transmission Mode flag.
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#define BBUSY 0x08 // Bus Busy flag.
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#define BLOST 0x04 // Bus Lost flag.
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#define ACK_RESP 0x02 // Not Acknowledge Response flag.
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#define SLV 0x01 // Slave Mode flag.
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SFR(S1DAT, 0xDE); // I2C Data Shift Register.
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SFR(S1ADR, 0xDF); // I2C Address Register (bit 0 not used).
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SFR(PSW, 0xD0); // Program Status Word.
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SBIT(CY, 0xD0, 7); // Carry Flag.
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SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag.
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SBIT(F0, 0xD0, 5); // User-Defined Flag.
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SBIT(RS1, 0xD0, 4); // Register Bank Select 1.
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SBIT(RS0, 0xD0, 3); // Register Bank Select 0.
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SBIT(OV, 0xD0, 2); // Overflow Flag.
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SBIT(P, 0xD0, 0); // Parity Flag.
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SFR(A, 0xE0);
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SFR(ACC, 0xE0); // Accumulator
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SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0.
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SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1.
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SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2.
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SBIT(ACC_3, 0xE0, 3); // Accumulator bit 3.
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SBIT(ACC_4, 0xE0, 4); // Accumulator bit 4.
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SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5.
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SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6.
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SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7.
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SFR(B, 0xF0); // B Register
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SBIT(B_0, 0xF0, 0); // Register B bit 0.
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SBIT(B_1, 0xF0, 1); // Register B bit 1.
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SBIT(B_2, 0xF0, 2); // Register B bit 2.
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SBIT(B_3, 0xF0, 3); // Register B bit 3.
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SBIT(B_4, 0xF0, 4); // Register B bit 4.
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SBIT(B_5, 0xF0, 5); // Register B bit 5.
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SBIT(B_6, 0xF0, 6); // Register B bit 6.
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SBIT(B_7, 0xF0, 7); // Register B bit 7.
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// PSD registers definition - by Jan Waclawek - wek at efton dot sk - May 2007
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// all defines here are with PSD_ prefix to identify them as PSD-related
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//
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// Based on uPSD33xx datasheet (preliminary) - Jan 2005, Table 79 at pages 145/146
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// and subsequent text
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// requires to have PSD_CSIOP defined to the base address of the PSD IO area,
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// as defined in PSDSoftExpress or CUPS
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#ifndef PSD_CSIOP
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#error PSD_CSIOP has to be #define-d (before #include-ing this file) to the base address of the PSD registers area, according to csiop setting in CUPS/PSDSoftExpress
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#else
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// -- Port A not available on 52-pin uPSD33xx devices
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SFRX(PSD_DATAIN_A, PSD_CSIOP+0x00); // MCU I/O Mode Port A Data In Register
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// reads 0 if pin is log.0, 1 if pin is log. 1
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// READ only
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SFRX(PSD_DATAOUT_A, PSD_CSIOP+0x04); // MCU I/O Mode Port A Data Out Register
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// write 0 to set pin to log. 0, 1 to set pin to log. 1
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// read back written value
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// reset default = 00
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SFRX(PSD_DIRECTION_A, PSD_CSIOP+0x06); // MCU I/O Mode Port A Direction Register
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// write 1 to set pin as output, 0 to set pin as input
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// read back written value
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// reset default = 00
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SFRX(PSD_DRIVE_A, PSD_CSIOP+0x08); // Select Open Drain or High Slew Rate for port A
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// PA0-PA3: write 0 to select standard push-pull CMOS output, 1 to select High Slew Rate push-pull CMOS output
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// PA4-PA7: write 0 to select standard push-pull CMOS output, 1 to select Open Drain output
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// reset default = 00
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SFRX(PSD_CONTROL_A, PSD_CSIOP+0x02); // Selects MCU I/O or Latched Address Out mode for port A
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// write 0 to select standard I/O pin, 1 to drive demultiplexed address signal on pin
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// read back written value
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// reset default = 00
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SFRX(PSD_OUTENABLE_A, PSD_CSIOP+0x0C); // Read state of Output Enable Logic on each I/O port driver of Port A
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// 1 - driver output is enabled, 0 - driver is off (high impedance)
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// READ only
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// -- for comment on individual registers, see above Port A
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SFRX(PSD_DATAIN_B, PSD_CSIOP+0x01); // MCU I/O Mode Port B Data In Register
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SFRX(PSD_DATAOUT_B, PSD_CSIOP+0x05); // MCU I/O Mode Port B Data Out Register
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SFRX(PSD_DIRECTION_B, PSD_CSIOP+0x07); // MCU I/O Mode Port B Direction Register
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SFRX(PSD_DRIVE_B, PSD_CSIOP+0x09); // Select Open Drain or High Slew Rate for port B
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// PB0-PB3: standard/High Slew Rate, PB4-PB7: standard/Open Drain
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SFRX(PSD_CONTROL_B, PSD_CSIOP+0x03); // Selects MCU I/O or Latched Address Out mode for port B
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SFRX(PSD_OUTENABLE_B, PSD_CSIOP+0x0D); // Read state of Output Enable Logic on each I/O port driver of Port B
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// -- for comment on individual registers, see above Port A
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// only pins PC2, PC3, PC4, PC7 available; other bits in registers are undefined
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SFRX(PSD_DATAIN_C, PSD_CSIOP+0x10); // MCU I/O Mode Port C Data In Register
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SFRX(PSD_DATAOUT_C, PSD_CSIOP+0x12); // MCU I/O Mode Port C Data Out Register
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SFRX(PSD_DIRECTION_C, PSD_CSIOP+0x14); // MCU I/O Mode Port C Direction Register
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SFRX(PSD_DRIVE_C, PSD_CSIOP+0x16); // Select Open Drain for port C
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SFRX(PSD_OUTENABLE_C, PSD_CSIOP+0x1A); // Read state of Output Enable Logic on each I/O port driver of Port C
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|
|
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// -- for comment on individual registers, see above Port A
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// only pins PD1, PD2 available (PD2 not available on 52-pin package); other bits in registers are undefined
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SFRX(PSD_DATAIN_D, PSD_CSIOP+0x11); // MCU I/O Mode Port D Data In Register
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SFRX(PSD_DATAOUT_D, PSD_CSIOP+0x13); // MCU I/O Mode Port D Data Out Register
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SFRX(PSD_DIRECTION_D, PSD_CSIOP+0x15); // MCU I/O Mode Port D Direction Register
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SFRX(PSD_DRIVE_D, PSD_CSIOP+0x17); // Select High Slew Rate for port D
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SFRX(PSD_OUTENABLE_D, PSD_CSIOP+0x1B); // Read state of Output Enable Logic on each I/O port driver of Port D
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|
|
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SFRX(PSD_IMC_A, PSD_CSIOP+0x0A); // Read to obtain logic state of Input Macrocells connected to Port A
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|
// READ only
|
|
SFRX(PSD_IMC_B, PSD_CSIOP+0x0B); // Read to obtain logic state of Input Macrocells connected to Port B
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|
SFRX(PSD_IMC_C, PSD_CSIOP+0x18); // Read to obtain logic state of Input Macrocells connected to Port C
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// only pins PC2, PC3, PC4, PC7 available; other bits in register are undefined
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SFRX(PSD_OMC_AB, PSD_CSIOP+0x20); // Read logic state of macrocells AB. Write to load macrocell AB flip-flops.
|
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SFRX(PSD_OMC_BC, PSD_CSIOP+0x21); // Read logic state of macrocells BC. Write to load macrocell BC flip-flops.
|
|
SFRX(PSD_OMCMASK_AB, PSD_CSIOP+0x22); // Write to set mask for macrocell AB.
|
|
// 1 blocks READs/WRITEs of OMF, 0 will pass OMF value
|
|
// Read back written value.
|
|
SFRX(PSD_OMCMASK_BC, PSD_CSIOP+0x23); // Write to set mask for macrocell BC.
|
|
|
|
// -- all three Power Management Register are set to 00 after PowerUp, but unchanged during reset (/RST)
|
|
SFRX(PSD_PMMR0, PSD_CSIOP+0xB0); // -- Power Management Register 0 - write/read
|
|
// bit 0 unused and should be set to 0
|
|
#define PSD_APD_ENA 0x02 // 0 - Automatic Power Down (APD) counter is disabled, 1 - APD enabled
|
|
// bit 2 unused and should be set to 0
|
|
#define PSD_TURBO_DISA 0x08 // 0 - PSD Turbo mode enabled, 1 - Turbo mode off, saving power
|
|
#define PSD_BLOCK_CLKIN_PLD 0x10 // 0 - CLKIN to PLD not blocked, 1 - no CLKIN to PLD Input Bus, saving power
|
|
#define PSD_BLOCK_CLKIN_OMC 0x20 // 0 - CLKIN to Output Macrocells not blocked, 1 - blocked, saving power
|
|
// bits 6 and 7 unused and should be set to 0
|
|
|
|
SFRX(PSD_PMMR2, PSD_CSIOP+0xB4); // -- Power Management Register 2 - write/read
|
|
// bits 0 and 1 unused and should be set to 0
|
|
#define PSD_BLOCK_WR_PLD 0x04 // 0 - /WR from 8032 to PLD Input Bus not blocked, 1 - blocked, saving power
|
|
#define PSD_BLOCK_RD_PLD 0x08 // 0 - /RD from 8032 to PLD Input Bus not blocked, 1 - blocked, saving power
|
|
#define PSD_BLOCK_PSEN_PLD 0x10 // 0 - /PSEN from 8032 to PLD Input Bus not blocked, 1 - blocked, saving power
|
|
#define PSD_BLOCK_ALE_PLD 0x20 // 0 - ALE from 8032 to PLD Input Bus not blocked, 1 - blocked, saving power
|
|
#define PSD_BLOCK_PC7_PDL 0x40 // 0 - input from Port C pin 7 to PLD Input Bus not blocked, 1 - blocked, saving power
|
|
// bit 7 unused and should be set to 0
|
|
|
|
SFRX(PSD_PMMR3, PSD_CSIOP+0xC7); // -- Power Management Register 3 - write/read
|
|
// bit 0 unused and should be set to 0
|
|
#define PSD_FORCE_PD 0x02 // 0 - APD counter, if enabled, will cause powerdown, 1 - powerdown will be entered immediately
|
|
// - once set, cleared only by reset condition
|
|
// bit 2 not defined by datasheet
|
|
// bits 3 to 7 unused and should be set to 0
|
|
|
|
SFRX(PSD_MAINPROTECT, PSD_CSIOP+0xC0); // -- Main Flash Memory Protection Definition
|
|
// bit 0 to bit 7 - sector 0 to sector 7 protection status
|
|
// - 1 - flash sector write protected, 0 - not write protected
|
|
// READ only
|
|
SFRX(PSD_ALTPROTECT, PSD_CSIOP+0xC2); // -- Secondary Flash Memory Protection Definition
|
|
// bit 0 to bit 3 - sector 0 to sector 3 protection status
|
|
// - 1 - flash sector write protected, 0 - not write protected
|
|
// bit 7 - Security Bit
|
|
// - 1 - device is secured against external reading and writing, 0 - not secured
|
|
// READ only
|
|
|
|
SFRX(PSD_PAGE, PSD_CSIOP+0xE0); // -- Memory Page Register
|
|
|
|
SFRX(PSD_VM, PSD_CSIOP+0xE2); // -- Memory Mapping Register
|
|
// Places PSD Module memories into 8032 Program Address Space
|
|
// and/or 8032 XDATA Address Space
|
|
// Default value of bits 0 to 4 is loaded from Non-Volatile
|
|
// setting as specified from PSDsoft Express upon any reset
|
|
// or power-up condition. The default value of these bits
|
|
// can be overridden by 8032 at run-time.
|
|
#define PSD_VM_SRAM_CODE 0x01 // 0 - SRAM not accessible as CODE (/PSEN) memory, 1 - SRAM accessible as CODE memory
|
|
#define PSD_VM_ALT_CODE 0x02 // 0 - secondary FLASH not accessible as CODE (/PSEN) memory, 1 - secondary FLASH accessible as CODE memory
|
|
#define PSD_VM_MAIN_CODE 0x04 // 0 - primary FLASH not accessible as CODE (/PSEN) memory, 1 - primary FLASH accessible as CODE memory
|
|
#define PSD_VM_ALT_XDATA 0x08 // 0 - secondary FLASH not accessible as XDATA (/RD/WR) memory, 1 - secondary FLASH accessible as XDATA memory
|
|
#define PSD_VM_MAIN_XDATA 0x10 // 0 - primary FLASH not accessible as XDATA (/RD/WR) memory, 1 - primary FLASH accessible as XDATA memory
|
|
// bits 5 and 6 unused
|
|
#define PSD_VM_PIO_EN 0x80 // 0 - disable, 1- enable peripheral I/O mode on Port A
|
|
|
|
// another terminology for FLASH - MAIN/ALTERNATIVE -> PRIMARY/SECONDARY
|
|
#define PSD_VM_PRI_CODE PSD_VM_MAIN_CODE
|
|
#define PSD_VM_SEC_CODE PSD_VM_ALT_CODE
|
|
#define PSD_VM_PRI_XDATA PSD_VM_MAIN_XDATA
|
|
#define PSD_VM_SEC_XDATA PSD_VM_ALT_XDATA
|
|
|
|
#endif
|
|
|
|
#endif //REG_UPSD33XX_H
|